Lower resolution HDTV receivers

• US 5,262,854 A
• Filed: 02/21/1992
• Issued: 11/16/1993
• Est. Priority Date: 02/21/1992
• Status: Expired due to Term

• Current Assignee: RCA Thomson Licensing Corporation
• Original Assignee: RCA Thomson Licensing Corporation
• Inventors: Ng, Sheau-Bao
• Primary Examiner(s): Chin, Tommy P.
• Assistant Examiner(s): LEE, RICHARD J
• Application Number:
  US07/839,161
• Time in Patent Office: 634 Days
• Field of Search: 358/105, 358/133, 358/135, 358/136
• US Class Current: 375/240.24
• CPC Class Codes: G06T 3/4084 in the transform domain, e.g. fast Fourier transform [FFT] domain scaling
• CPC Class Codes: H04N 19/00 Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• CPC Class Codes: H04N 19/124 Quantisation
• CPC Class Codes: H04N 19/132 Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/577 Motion compensation with bidirectional frame interpolation, i.e. using B-pictures
• CPC Class Codes: H04N 19/59 involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 19/60 using transform coding
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/70 characterised by syntax aspects related to video coding, e.g. related to compression standards
• CPC Class Codes: H04N 19/90 using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
• CPC Class Codes: H04N 21/236 Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream multiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/434 Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00

Abstract

A receiver for receiving block coded HDTV compressed digital video signals decimates the data in each block to produce NTSC resolution images but with a significant savings in receiver hardware.

Claims

1. Apparatus for decompressing compressed video data occurring in blocks representing respective image areas of successive frames with a first spatial resolution, and wherein each frame consists of a plurality of distinct image areas, said apparatus including memory means for storing decompressed video data, means for decompressing respective blocks of data to produce decompressed video signal representing corresponding image areas with a second spatial resolution lower than said first spatial resolution, and means for storing said decompressed video signal in said memory means.

2. The apparatus set forth in claim 1 wherein said compressed video data occurs in blocks of codewords representing M by M pixels, and said decompression means produces blocks of N by N pixels representing said image areas, where M and N are integers with M greater than N.

3. The apparatus set forth in claim 1 wherein said blocks of compressed video data consist of coefficients generated by performing a discrete cosine transform over M by M matrices of pixel values, and said means for decompressing includes inverse discrete cosine transform means for performing inverse discrete cosine transforms over N by N matrices of discrete cosine transform coefficients, and means responsive to said coefficients generated by performing a discrete cosine transform over M by M matrices of pixel values for providing N by N matrices of coefficients to said means for performing inverse discrete cosine transforms for respective image areas, where M and N are integers and M is greater than N.

4. The apparatus set forth in claim 1 wherein said means for decompressing respective blocks of data includes;

a first decimator having an input terminal for receiving said blocks of compressed video signal and having an output terminal, said first decimator for providing N by N matrices of compressed video signal values from M by M matrices of compressed video signal values.

summing means, having a first input terminal coupled to the output terminal of said first decimator, having a second input terminal, and having an output terminal coupled to said memory means;

interpolation means having an input terminal coupled to said memory means and having an output terminal, for generating M by M matrices of pixel values from N by N matrices of pixel values accessed from said memory means;

a video signal motion compensated predictor having an input terminal coupled to the output terminal of said interpolation means, and having an output terminal; and

a second decimator coupled between said video signal motion compensated predictor and the second input terminal of said summing means, for generating N by N matrices of pixel values from M by M matrices of pixel values provided from said video signal motion compensated predictor.

5. The apparatus set forth in claim 4 wherein said compressed video data includes motion vectors which are coupled to said video signal motion compensated predictor for conditioning said video signal motion compensated predictor to generate memory read addresses for accessing respective matrices of pixel values, and a least significant bit of said memory read addresses is coupled to control said interpolation means.

6. The apparatus set forth in claim 1 wherein said means for decompressing respective blocks of data includes;

summing means, having a first input terminal coupled for receiving said blocks of compressed video data, having a second input terminal, and having an output terminal;

a decimator having an input terminal coupled to the output terminal of said summing means and having an output terminal coupled to an input terminal of said memory means, said decimator for providing N by N matrices of values from M by M matrices of values provided from said summing means;

interpolation means having an input terminal coupled to said memory means and having an output terminal, for generating M by M matrices of pixel values from N by N matrices of pixel values accessed from said memory means;

a video signal motion compensated predictor having an input terminal coupled to the output terminal of said interpolation means, and having an output terminal to the second input terminal of said summing means.

7. The apparatus set forth in claim 6 wherein said compressed video data includes motion vectors which are coupled to said video signal motion compensated predictor for conditioning said video signal motion compensated predictor to generate memory read addresses for accessing respective matrices of pixel values, and a least significant bit of said memory said addresses is coupled to control said interpolation means.

8. The apparatus set forth in claim 1 wherein said means for decompressing respective blocks of data includes;

summing means, having a first input terminal coupled for receiving said blocks of compressed video data, having a second input terminal, and having an output terminal;

a decimator having an input terminal coupled to the output terminal of said summing means and having an output terminal coupled to an input terminal of said memory means, said decimator for providing N by N matrices of values from M by M matrices of values provided from said summing means;

a video signal motion compensated predictor having an input terminal coupled to said memory means, and having an output terminal; and

interpolation means having an input terminal coupled to the output terminal of said video signal motion compensated predictor and having an output terminal coupled to the second input terminal of said summing means, for generating M by M matrices of pixel values from N by N matrices of pixel values provided by said video signal motion compensated predictor.

9. The apparatus set forth in claim 8 wherein said compressed video data includes motion vectors which are coupled to said video signal motion compensated predictor for conditioning said video signal motion compensated predictor to generate memory read addresses for accessing respective matrices of pixel values, and at least significant bit of said memory read addresses is coupled to control said interpolation means.

10. The apparatus set forth in claim 1 wherein said blocks of compressed video data consist of coefficients generated by performing a transform over M by M matrices of pixel values, and said means for decompressing includes inverse transform means for performing inverse transforms over N by N matrices of transform coefficients, and means, responsive to said coefficients generated by performing a transform over M by M matrices of pixel values, for providing N by N matrices of coefficients to said means for performing inverse transforms for respective image areas, where M and N are integers and M is greater than N.

11. The apparatus set forth in claim 10 wherein said apparatus further includes:

summing means, having a first input terminal coupled to said inverse transform means, having a second input terminal, and having an output terminal coupled to said memory means; and

a video signal motion compensated predictor coupled between said memory means and said second input of said summing means.

12. The apparatus set forth in claim 11 further including;

interpolation means coupled between said memory means and said video signal motion compensated predictor, for generating M by M matrices of pixel values from N by N matrices of pixel values accessed from said memory means; and

a decimator coupled between said video signal motion compensated predictor and the second input terminal of said summing means, for generating N by N matrices of pixel values from M by M matrices of pixel values provided from said video signal motion compensated predictor.

13. The apparatus set forth in claim 12 wherein said compressed video data includes motion vectors which are coupled to said video signal motion compensated predictor for conditioning said video signal motion compensated predictor to generate memory read addresses for accessing respective matrices of pixel values, and a least significant bit of said memory read addresses is coupled to control said interpolation means.

14. Apparatus for decompressing compressed video data occurring in blocks representing respective image areas of successive frames with a first spatial resolution to produce decompressed video signal representing corresponding image areas with a second spatial resolution lower than said first spatial resolution, said block of video data including M×

N matrices of transform coefficients representing M×

N matrices of pixel values, and including motion vectors having a spatial resolution at least equal to the first spatial resolution of said pixels, said apparatus comprising;

a source of blocks of M×

N matrices of transform coefficients;

means including inverse transform means responsive to said blocks of M×

N transform coefficients for generating corresponding S×

R matrices of values (M, N, S and R are integers with M×

N>

S×

R);

means including a motion compensated predictor responsive to said R×

R matrices of values and said motion vectors for generating S×

R matrices of pixel values representing respective image areas with said second spatial resolution, said motion compensated predictor including means for substantially conforming spatial resolutions of the motion vectors and the S×

R matrices of values; and

memory means for storing respective S×

R matrices of pixel data.

15. The apparatus set forth in claim 14 wherein said means including a motion compensated predictor further includes:

summing means, having a first input terminal coupled to said inverse transform means, having a second input terminal coupled to an output terminal of said motion compensated predictor, and having an output terminal coupled to said memory means.

16. The apparatus set forth in claim 14 wherein said means including inverse transform means further includes:

masking apparatus, coupled to said source of blocks of M×

N matrices of transform coefficients, for providing only S times R coefficients to said inverse transform means; and

wherein said inverse transform means is arranged to process S×

R coefficients to provide S×

R transformed values.

17. The apparatus set forth in claim 14 wherein said means including inverse transform means further includes:

means coupled to said source of blocks of M×

N matrices of transform coefficients applied to said inverse transform means; and

wherein

said inverse transform means provides M×

N matrices of transformed values for corresponding blocks of M×

N coefficients; and

decimation means coupled to said inverse transform means for decimating M×

N matrices of transformed values to said S×

R matrices of values.

18. The apparatus set forth in claim 14 wherein said means including a motion compensated predictor further includes:

interpolation means associated with said motion compensated predictor for generating M×

N matrices of pixel values from S×

R matrices of pixel values accessed from said memory means.

19. The apparatus set forth in claim 18 wherein said means including a video signal motion compensated predictor further includes:

a decimator coupled between said video signal motion compensated predictor and the second input terminal of said summing means, for providing S×

R matrices of pixel values to said summing means.

20. The apparatus set forth in claim 18 wherein said motion vectors are coupled to said motion compensated predictor for conditioning said motion compensated predictor to generate memory read addresses for accessing respective matrices of pixel values, and a least significant bit of said memory read addresses is coupled to control said interpolation means.