Power converter

• US 5,262,932 A
• Filed: 03/03/1992
• Issued: 11/16/1993
• Est. Priority Date: 03/04/1991
• Status: Expired due to Fees

• Current Assignee: Cooperheat International Limited
• Original Assignee: Cooperheat International Limited
• Inventors: Stanley, David L., Petkov, Roumen D., Hadjivassilev, Stefan T., Leisten, Michael J., Lefedjiev, Adrian K.
• Primary Examiner(s): Stephan, Steven L.
• Assistant Examiner(s): Davidson, Ben
• Application Number:
  US07/845,186
• Time in Patent Office: 623 Days
• Field of Search: 363/17, 363/98, 363/56, 363/58, 363/41, 363/132, 363/26, 323/272
• US Class Current: 363/26
• CPC Class Codes: H02M 3/33573 Full-bridge at primary side of an isolation transformer

Abstract

In one embodiment, a solid state DC power supply includes an inverter (30) having two half-bridges (32, 34) in which are provided pairs of MOSFETS (Q5-Q12) used as switching elements. An output transformer (60) and a rectifier (85) are connected to output terminals (T60). A feedback path includes switching control means (40) separate primary and secondary drive means (10, 20) supplying drive pulses to the switching means (Q5-Q12) in the inverter (30). The secondary drive means (12, 13) amplifies the pulse output of the primary drive means (11) in order to improve the switching speed of the inverter (30). Current detection is provided by a transformer (70) connected to switching (40). The primary and secondary drive means receive pulses from a pulse width modulator (IC5) the output of which is isolated by transformers (TX1, TX2). In a modification, a power converter in the form of a DC power supply includes parallel MOSFET (M) and IGBT (I) switch pairs in each arm of a full wave bridge configuration. The IGBT (I) has lower conduction loss and higher switching loss than the MOSFET (M) so that, when appropriately timed driving pulses are applied, the IGBT (I) carries current in most of a conduction period and the MOSFET (M) switches off whilst a low voltage is maintained across the IGBT (I). This reduces conduction and switching losses to a minimum.

Claims

1. A power converter comprising:

an inverter including a bridge configuration having an input, an output, a plurality of arms, and respective switching means in its arms;

each of said switching means comprising a parallel combination of first and second devices, said first device having a lower conduction loss than said second device and a higher switching loss than said second device;

switching control means connected in a feedback path from said output to said input for generating switching signals to control the operation of said switching means, said switching control means including means for monitoring current and voltage generated by the power converter and a pulse width modulator having inputs connected to said monitoring means, said pulse width modulator also having isolated outputs for providing said switching signals;

said pulse width modulator being responsive to the monitoring means to generate switching signals for maintaining substantially constant the current or voltage available from the power converter; and

drive means for each bridge arm including independent buffer stages and further including, for each parallel combination of said first and second devices, first and second isolated channels and a latch, said first channel transmitting information concerning a required switch time from said switching control means to said latch, said second channel transmitting information concerning the current state of the buffer stages back to the switching control means for comparison with the required switching state.

said drive means providing independent drive signals, in response to respective switching signals, wherein differentiated gating wave forms are used which have very short positive and negative impulses, said impulses being separated and then applied to the latch which in turn operates the respective buffer states for independently driving said first and second devices at predetermined times to that (a) said first device carries most of the current in its bridge arm during a conduction period, (b) said second device is maintained on when said first device is switched off towards the end of the conduction period and (c) said second device is subsequently switched off, whereby most heat, due to conduction loss, is generated in said first device during the conduction period and most heat, due to switching loss, is generated in said second device while switching off.

2. A power converter according to claim 1, in which the said first and second devices are respectively an IGBT and a MOSFET.

3. A power converter according to claim 1, further comprising a timing pulse generator which is driven by said pulse width modulator and which includes delay means to provide respective switching signals for generating the independent drive signals.

4. A power converter according to claim 1 in which all the said drive means are connected to a separate auxiliary switch mode power supply.

5. A power converter comprising:

input terminals for connection to a high voltage alternating supply;

an inverter including rectification means providing a rectified DC supply, said rectification means being connected to said input terminals and including a pair of half-bridge circuits connected in series across the rectified DC supply, each half-bridge circuit having arms including parallel connected IGBT and MOSFET devices, said IGBT having a lower conduction loss than said MOSFET and a higher switching loss than said MOSFET;

an output transformer/rectifier means connected between center points of said half-bridge circuits via a series capacitor, said output transformer/rectifier means having output terminals for providing a low voltage DC power supply;

a feedback path connected between said output terminals and control terminals of said IGBT and MOSFET devices, said feedback path including switching control means for generating switching signals for switching the IGBT and MOSFET in each respective arm ON together, and for switching said IGBT OFF before said MOSFET so that (a) said IGBT carries most of the current in its respective arm during a conduction period, (b) said MOSFET is maintained ON when said IGBT is switched OFF towards the end of said conduction period, and (c) said MOSFET is subsequently switched OFF;

the arrangement being such that most heat, due to conduction loss, is generated in said IGBT during the conduction period and most heat, due to switching loss, is generated in said MOSFET while switching OFF, said switching control means further providing a dead time between the end of one conduction period and the start of the next conduction period for each of said arms;

said switching control means comprising a timing pulse generator which is driven by said pulse width modulator and which includes delay means to provide respective switching signals for generating the independent drive signals for both said half-bridge circuits, so that (1) corresponding parallel connected IGBT and MOSFET devices, in opposite arms of each half-bridge circuit, are synchronously switched, and (ii) opposite arms are alternately switched, and further including means for monitoring current and voltage generated by the power converter and a pulse width modulator having inputs connected to said monitoring means, said pulse modulator also having isolated outputs for providing said switching signals;

said pulse width modulator being responsive to the monitoring means to generate said switching signals whereby the current or voltage available from the power converter is maintained substantially constant.

6. A power converter according to claim 5 in which the drive means for each bridge arm includes independent buffer stages and further includes, for each parallel combination of said first and second devices, first and second isolated channels and a latch, said first channel transmitting information concerning a required switching state from said switching control means to said latch, said second channel transmitting information concerning the current state of the buffer stages back to the switching control means for comparison with the required switching state.

7. A power inverter according to claim 6 wherein differentiated gating waveforms are used which have very short positive and negative impulses, said impulses being separated and then applied to the latch which in turn operates the respective buffer states for driving said first and second devices.

8. A power converter according to claim 7 including a feedback protection circuit which receives information concerning the current state of all of said switching means, said information including a first pulse at the beginning of the conduction interval of the switching means, said feedback protection circuit also receiving a clock pulse from the pulse width modulator and being responsive to the presence of said first pulse to maintain said switching signals and being responsive to said clock pulse, in the absence of said first pulse, to suppress said switching signals.

9. A power converter according to claim 8 in which all the said drive means are connected to a separate auxiliary switch mode power supply.