Representation and processing of hierarchical block designs

• US 5,262,959 A
• Filed: 12/07/1990
• Issued: 11/16/1993
• Est. Priority Date: 12/07/1990
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Company (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Chkoreff, Lawrence P.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US07/624,007
• Time in Patent Office: 1,075 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/103
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

The disclosed invention is a method of determining one or more parameters associated with the hierarchical circuit design. The method comprises the step of: (a) constructing a data structure representing the hierarchical circuit design; (b) synthesizing a list of attributes associated with each block in the design, the synthesis starting at the lowest level nonleaf blocks in the hierarchy and proceeding through all higher level blocks in the design; and (c) based upon the list of attributes determining in the step (b), analyzing the data structure and determining the parameter. One of the parameters determined is the delay associated with each leaf component.

Claims

1. In a computer aided engineering system, a method of determining at least one parameter associated with a hierarchical circuit design, the hierarchical circuit having at least one nonleaf component, the nonleaf component having at least one leaf component, and each component having at least one input port and one output port, the method comprising the steps of:

(a) constructing a data structure representing the hierarchical circuit design, each nonleaf component of the circuit represented in the data structure by a block of data, each block of data comprising (1) a list of ports of the nonleaf component, (2) a list of components composing said nonleaf component, and (3) a partitioned list of ports of said components composing said nonleaf component, said partitioned list of ports being partitioned into classes representing nets to which said ports are connected;

(b) synthesizing, based at least upon the data structure constructed in step (a), a list of attributes associated with each block in the design;

(c) analyzing, based at least upon the list of attributes synthesized in step (b), the data structure and determining said parameter; and

(d) providing an indication of the result of step (c).

2. Method of claim 1 wherein said parameter to be determined is a delay parameter associated with each leaf component.

3. Method of claim 2 wherein step (b) further comprises:

(i) determining a gate count ("G_L ") for each leaf component represented in the data structure;

(ii) calculating a gate count ("G_NL ") for each nonleaf component represented in the data structure;

(iii) determining a connection count ("N_L ") and pin capacitance ("C_L ") for each port of each leaf component represented in the data structure;

(iv) calculating a connection count ("N_NL ") and pin capacitance ("C_NL ") for each net represented in the data structure;

(v) determining a connection count ("N_NPL ") and pin capacitance ("C_NLP ") for each port of each nonleaf component represented in the data structure;

(vi) determining an intrinsic capacitance ("I") for each net represented in the data structure; and

(vii) determining a total capacitance ("T") for each net represented in the data structure.

4. Method of claim 3 wherein G_L is predefined.

5. Method of claim 3 wherein G_NL for each nonleaf component is equal to the sum of the gate counts G_L Of all leaf components listed in the block for which the synthesis is to be performed.

6. Method of claim 3 wherein the connection count N_L and pin capacitance C_L for each port of each leaf block is predefined.

7. Method of claim 3 wherein the connection count N_NL for each net is equal to the sum of the connection counts N_L of all ports connected to the net for Which N_NL is to be calculated.

8. Method of claim 3 wherein the pin capacitance C_NL for each net is equal to the sum of the pin capacitances C_L of all ports connected to the net for Which C_NL is to be calculated.

9. Method of claim 3 wherein the pin capacitance C_NLP for each port of each nonleaf component is equal to the pin capacitance C_NL of a net associated with that port.

10. Method of claim 3 wherein the connection count N_NLP for each port of each nonleaf component is equal to the connection count N_NL of a net associated with that port.

11. Method of claim 3 wherein the intrinsic capacitance I of each internal net is a function of at least the values of N_NL and G_NL associated with that net.

12. Method of claim 3 wherein the total capacitance T of each net is equal to the sum of C_NL and I associated with that net.

13. Method of claim 2 wherein step (c) further comprises:

(i) determining an attribute ("T") associated with each port of each nonleaf component represented by the data structure; and

(ii) determining the attribute T associated with each net and port represented in the data structure.

14. Method of claim 13 wherein T represents the total capacitance.

15. Method of claim 13 wherein step (c) further comprises:

(iii) determining a delay parameter associated with an output port of each leaf component represented in the data structure.

16. Method of claim 15 wherein step (iii) comprises:

(1) determining a maximum capacitance ("C_i ") of any net connected to an input port of at least one leaf component;

(2) determining a capacitance ("C_o ") of an output port of the leaf component for which C_i was determined in step (1); and

(3) calculating the delay parameter associated with the output port for which C_o was determined in step (2), said delay parameter being a function of at least C_o and C_i.

17. In a computer aided engineering system, a method of determining at least one parameter associated with a hierarchical circuit design, the hierarchical circuit having at least one nonleaf component, the nonleaf component having at least one leaf component, and each component having at least one input port and one output port, the method comprising the steps of:

(a) constructing a data structure representing the hierarchical circuit design, each nonleaf component of the circuit represented in the data structure by a block of data, each block of data comprising (1) a list of ports of the nonleaf component, (2) a list of components composing said nonleaf component, and (3) a partitioned list of ports of said components composing said nonleaf component, said partitioned list of ports being partitioned into classes representing nets to which said ports are connected;

(b) synthesizing, based at least upon the data structure constructed in step (a), a list of attributes associated with each block in the design, the synthesis comprising;

(i) determining a gate count ("G_L ") for each leaf component represented in the data structure;

(ii) calculating a gate count ("G_NL ") for each nonleaf component represented in the data structure;

(iii) determining a connection count ("N_L ") and pin capacitance ("C_L ") for each port of each leaf component represented in the data structure;

(iv) calculating a connection count ("N_NL ") and pin capacitance ("C_NL ") for each net represented in the data structure;

(v) determining a connection count ("N_NPL ") and pin capacitance ("C_NLP ") for each port of each nonleaf component represented in the data structure;

(vi) determining an intrinsic capacitance ("I") for each net represented in the data structure; and

(vii) determining a total capacitance ("T") for each net represented in the data structure;

(c) analyzing, based at least upon the list of attributes synthesized in step (b), the data structure and determining said parameter; and

(d) providing an indication of the result of step (c).

18. Method of claim 17 wherein G_L is predefined.

19. Method of claim 17 wherein G_NL for each nonleaf component is equal to the sum of the gate counts G_L of all leaf components represented by the block for Which the synthesis is to be performed.

20. Method of claim 17 wherein the connection count N_L and pin capacitance C_L associated with each port of each leaf component is predefined.

21. Method of claim 17 wherein the connection count N_NL for each net is equal to the sum of the connection counts N_L of all ports connected to the net for which N_NL is to be calculated.

22. Method of claim 17 wherein the pin capacitance C_NL associated with each net is equal to the sum of the pin capacitances C_L of all ports connected to the net for which C_NL is to be calculated.

23. Method of claim 17 wherein the pin capacitance C_NLP associated with each port of each nonleaf component is equal to the pin capacitance C_NL of a net associated with that port.

24. Method of claim 17 wherein the connection count N_NLP associated with each port of each nonleaf block is equal to the connection count N_NL of a net associated with that port.

25. Method of claim 17 wherein the intrinsic capacitance I of each internal net is a function of at least the values of N_NL and G_NL associated with that net.

26. Method of claim 17 wherein the total capacitance T of each net is equal to the sum of C_NL and I associated with that net.

27. In a computer aided engineering system, a method of determining a delay parameter associated with a hierarchical circuit design, the hierarchical circuit having at least one nonleaf component, the nonleaf component having at least one leaf component, and each component having at least one input port and one output port, the method comprising the steps of:

(a) constructing a data structure representing the hierarchical circuit design, each nonleaf component of the circuit represented in the data structure by a block of data, each block of data comprising (1) a list of ports of the nonleaf component, (2) a list of components composing said nonleaf component, and (3) a partitioned list of ports of said components composing said nonleaf component, said partitioned list of ports being partitioned into classes representing nets to which said ports are connected;

(b) synthesizing, based at least upon the data structure constructed in step (a), a list of attributes associated with each block in the design;

(c) analyzing, based at least upon the list of attributes synthesized in step (b), the data structure and determining said delay parameter, the analysis comprising;

(i) determining an attribute ("T") associated with each port of each nonleaf component represented by the data structure; and

(ii) determining the attribute T associated with each net and port represented in the data structure; and

(d) providing an indication of the result of step (c).

28. Method of claim 27 wherein T represents the total capacitance.

29. Method of claim 27 wherein step (c) further

(iii) determining a delay delay parameter associated with each output port of each leaf component.

30. Method of claim 29 wherein step (iii) comprises:

(1) determining a maximum capacitance ("C_i ") of any net connected to any input port of at least one leaf component;

(2) determining a capacitance ("C_o ") of an output port of the leaf component for which C_i was determined in step (1); and

(3) calculating the delay parameter associated with the output port for which C_o was determined in step (2), said delay parameter being a function of at least C_o and C_i.

31. In a computer aided engineering system, a method of determining a delay parameter associated with a hierarchical circuit design, the hierarchical circuit having at least one nonleaf component, the nonleaf component having at least one leaf component, and each component having at least one input port and one output port, the method comprising the steps of:

(a) constructing a data structure representing the hierarchical circuit design, each nonleaf component of the circuit represented in the data structure by a block of data, each block of data comprising (1) a list of ports of the nonleaf component, (2) a list of components composing said nonleaf component, and (3) a partitioned list of ports of said components composing said nonleaf component, said partitioned list of ports being partitioned into classes representing nets to which said ports are connected;

(b) synthesizing, based at least upon the data structure constructed in step (a), a list of attributes associated with each block in the design, the synthesis comprising;

(i) determining a gate count ("G_L ") for each leaf component represented in the data structure;

(ii) calculating a gate count ("G_NL ") for each nonleaf component represented in the data

(iii) determining a connection count ("N_L ") and pin capacitance ("C_L ") for each port of each leaf component represented in the data structure;

(iv) calculating a connection count ("N_NL ") and pin capacitance ("C_NLP ") for each net represented in the data structure;

(v) determining a connection count ("N_NPL ") and pin capacitance ("C_NLP ") for each port of each nonleaf component represented in the data structure;

(vi) determining an intrinsic capacitance ("I") for each net represented in the data structure; and

(vii) determining a total capacitance ("T") for each net represented in the data structure;

(c) analyzing, based at least upon the list of attributes synthesized in step (b), the data structure and determining said delay parameter, the analysis comprising;

(i) determining an attribute ("T") associated with each port of each nonleaf component represented by the data structure; and

(ii) determining the attribute T associated with each net and port represented in the data structure; and

(d) providing an indication of the result of step (c).

32. Method of claim 31 wherein G_L is predefined.

33. Method of claim 31 wherein G_NL associated with each nonleaf component is equal to the sum of the gate counts G_L of all leaf components represented by the block for which the synthesis is to be performed.

34. Method of claim 31 wherein the connection count N_L and pin capacitance C_L for each port of each leaf component is predefined.

35. Method of claim 31 wherein the connection count N_NL for each net is equal to the sum of the connection counts N_L of all ports connected to the net for which N_NL is to be calculated.

36. Method of claim 31 wherein the pin capacitance C_NL for each net is equal to the sum of the pin capacitances C_L of all ports connected to the net for which C_NL is to be calculated.

37. Method of claim 31 wherein the pin capacitance C_NLP for each port of each nonleaf component is equal to the pin capacitance C_NL of a net associated with that port.

38. Method of claim 31 wherein the connection count N_NLP for each port of each nonleaf component is equal to the connection count N_NL of a net associated with that port.

39. Method of claim 31 wherein the intrinsic capacitance I is a function of at least the values of N_NL and G_NL associated with the net for which I is to be determined.

40. Method of claim 31 wherein the total capacitance T of each net is equal to the sum of C_NL and I associated with that net.

41. Method of claim 31 wherein step (c) further comprises:

(iii) determining a delay delay parameter associated with each output port of each leaf component.

42. Method of claim 41 wherein step (iii) comprises:

(1) determining a maximum capacitance ("C_i ") of any net connected to an input port of at least

(2) determining a capacitance ("C_o ") of an output port of the leaf component for which C_i was determined in step (1); and

(3) calculating the delay parameter associated with the output port for which C_o was determined in step (2), said delay parameter being a function of at least C_o and C_i.

43. Method of claim 31 wherein the data structure constructed in step (a) further comprises:

(4) a list of types indicative of the respective functions performed by the components comprising the nonleaf block.