High performance architecture for image processing
First Claim
1. A logical computer architecture for image and signal processing, and other related computations, using a data flow concept for performing operations of an image algebra having an algebraic set of operators;
- wherein the architecture comprises three tightly coupled processing components;
a spatial configuration processor (process S), a weighting processor using a point-wise operation (process W), and an accumulation processor (process A), wherein the data flow and image processing operations are directed by a control buffer and pipelined to each of said three processing components;
wherein the spatial configuration processor has an input for an original image and an input for a template, and in operation uses a step-wise discrete convolution of the original input image with each template location, with a unit value assigned to a template element for each convolution, a result of each convolution being a shift of an input image element, providing an output of the spatial configuration processor which is coupled to the weighting processor;
wherein the output of the spatial configuration processor is combined point-wise in the weighting processor, using an appropriate binary associative operator from the algebraic set of operators, with the value of the respective template element, the operation of the weighting processor being an array process execution using said appropriate binary associative operator, the weighting processor having an output coupled to the accumulation processor;
wherein the output of the weighting processor is accumulated point-wise in the accumulation processor, using an appropriate global reduce operator from the algebraic set of operators, the accumulation processor having an accumulator memory which, once the final template element is processed, contains the result of a generalized matrix product defined in the image algebra.
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Abstract
The logical computer architecture is specifically designed for image processing, and other related computations. The architecture is a data flow concept comprising three tightly coupled components: a spatial configuration processor, a point-wise operation processor, and a accumulation operation processor. The data flow and image processing operations are directed by the control buffer and pipelined to each of the three processing components. The image processing operations are defined by an image algebra capable of describing all common image-to-image transformations. The merit of this architectural design is how elegantly it handles the natural decomposition of algebraic functions into spatially distributed, point-wise operations. The effect of this particular decomposition allows convolution to be computed strictly as a function of the number of elements in the template (mask, filter, etc.) instead of the number of pixels in the image. Thus, a substantial increase in throughput is realized. The logical architecture may take any number of physical forms, including a hybrid electro-optical implementation, and an all digital implementation. The potential utility of this architectural design lies in its ability to control all the arithmetic and logic operations of the image algebra'"'"'s generalized matrix product. This is the most powerful fundamental formulation in the algebra, thus allowing a wide range of applications.
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Citations
7 Claims
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1. A logical computer architecture for image and signal processing, and other related computations, using a data flow concept for performing operations of an image algebra having an algebraic set of operators;
- wherein the architecture comprises three tightly coupled processing components;
a spatial configuration processor (process S), a weighting processor using a point-wise operation (process W), and an accumulation processor (process A), wherein the data flow and image processing operations are directed by a control buffer and pipelined to each of said three processing components;wherein the spatial configuration processor has an input for an original image and an input for a template, and in operation uses a step-wise discrete convolution of the original input image with each template location, with a unit value assigned to a template element for each convolution, a result of each convolution being a shift of an input image element, providing an output of the spatial configuration processor which is coupled to the weighting processor; wherein the output of the spatial configuration processor is combined point-wise in the weighting processor, using an appropriate binary associative operator from the algebraic set of operators, with the value of the respective template element, the operation of the weighting processor being an array process execution using said appropriate binary associative operator, the weighting processor having an output coupled to the accumulation processor; wherein the output of the weighting processor is accumulated point-wise in the accumulation processor, using an appropriate global reduce operator from the algebraic set of operators, the accumulation processor having an accumulator memory which, once the final template element is processed, contains the result of a generalized matrix product defined in the image algebra. - View Dependent Claims (2, 3, 4, 5, 6, 7)
- wherein the architecture comprises three tightly coupled processing components;
Specification