Non-volatile memory device capable of storing multi-state data

• US 5,262,984 A
• Filed: 07/28/1989
• Issued: 11/16/1993
• Est. Priority Date: 07/29/1988
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kobayashi, Shinichi, Noguchi, Kenji, Toyama, Tsuyoshi
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): Lane, Jack A.
• Application Number:
  US07/386,484
• Time in Patent Office: 1,572 Days
• Field of Search: 365/184, 365/185, 365/104, 365/45, 365/49, 365/168
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

The input data comprising binary data to be stored are converted into multi-state data. A voltage of a level based on the converted multi-state data is applied to a source region to perform write operation to a memory transistor. As a result, the threshold voltage of the transistor is set to a value corresponding to the potential of the source region. In read operation a drain current generated in the memory transistor is detected and the multi-state data corresponding to the current are obtained. These multi-state data are converted into binary data to be outputted as output data.

Claims

1. A non-volatile memory device capable of storing multi-state data having more than two states based on a threshold voltage, said multi-stage data corresponding to binary data, comprising:

an input data converting means for converting N (a natural number larger than

     1) binary signals into 2^N multi-state data to be stored and including constant voltage generating means for generating 2^N values of constant voltage corresponding to the 2^N multi-state data;

an output data converting means for converting said stored multi-state data into binary signals;

a drain electrode, a source electrode and a control gate electrode;

a floating gate to and out of which electric charge is injected or subtracted, said drain, source and control gate electrodes provided around said floating gate to constitute a memory transistor for storing said multi-state data, and said drain electrode and said source electrode are formed on a semiconductor substrate;

charge injecting means for injecting electric charge into said floating gate,

said charge injecting means including

first voltage applying means for applying zero potential to said control gate electrode and to said semiconductor substrate and for applying positive high voltage to said drain electrode in a data write operation, and

second voltage applying means for applying zero potential to said drain electrode, to said source electrode and to said semiconductor substrate, and for applying positive high voltage to said control gate electrode in a data erase operation; and

control means for controlling the amount of electric charge to be injected by said charge injecting means, said control means including means for applying one of said 2^N values of constant voltage generated by said constant voltage generating means to said source electrode to control charge injected into said floating gate during a write operation, wherein

said threshold voltage of said memory transistor is determined based on the injected amount of electric charge.

2. A non-volatile memory device according to claim 1, further comprising data reading means for reading data, wherein said data reading means includes

third voltage applying means for applying zero potential to said control gate electrode and to said source electrode and for applying a predetermined positive voltage to said drain electrode in a data read operation,

detecting means for detecting a current generated by said third voltage applying means between said source electrode and said drain electrode through said semiconductor substrate, and

signal generating means for generating an output signal according to a current detected by said detecting means.

3. A non-volatile memory device according to claim 2, wherein said signal generating means comprises:

voltage generating means for generating M (2^N . . . N;

a natural number larger than

     1) values of voltage corresponding to M values of the detected currents, and

binary signal generating means for generating √

M binary signals corresponding to said M values of voltage provided by said voltage generating means using (M-1) predetermined voltages.

4. A non-volatile memory device according to claim 1, wherein

a plurality of said floating gates and said charge injecting means are arranged on the non-volatile memory device, and

each of said charge injecting means is connected to a common voltage source and includes voltage source releasing means for releasing the connections with said common voltage source when the injection of electric charge into each of said floating gates by each of said charge injecting means has been stopped.

5. A non-volatile memory device according to claim 1, wherein

a plurality of floating gates and said charge injecting means are arranged on the non-volatile memory device, and

each of said individual electric charge injecting means is connected to a common voltage source and includes voltage source releasing means for releasing the connections with said common voltage source when the injection of electric charge into each of said floating gates by each of said charge injecting means has been stopped.

6. A non-volatile memory device according to claim 5, wherein said voltage source releasing means comprises:

detecting means for detecting a current generated between said source electrode and said drain electrode through said semiconductor substrate when the injection of electric charge into said floating gate electrode in said data write operation has been stopped, and

switching means for cutting off the connection with said common voltage source in response to an output detected by said detecting means.

7. A non-volatile memory device capable of storing multi-state data having more than two states based on a threshold voltage comprising:

input data converting means for converting N (a natural number larger than

     1) binary signals into 2^N multi-state data to be stored and including constant voltage generation means for generating 2N values of constant voltage corresponding to the 2^N multi-state data;

a drain electrode, a source electrode, and a control gate electrode;

a floating gate to and out of which electric charge is injected or subtracted, said drain, source and control gate electrodes provided around said floating gate electrode to constitute a memory transistor, and said drain electrode and said source electrode are formed on a semiconductor substrate;

charge injecting means for injecting electric charge into said floating gate, said charge injecting means including

first voltage applying means for applying zero potential to said control gate electrode and to said semiconductor substrate and for applying positive high voltage to said drain electrode in a data write operation, and

second voltage applying means for applying zero potential to said drain electrode, to said source electrode and to said semiconductor substrate, and for applying positive high voltage to said control gate electrode in a data erase operation; and

control means for controlling the amount of electric charge to be injected by said charge injecting means said control means including means for applying one of said 2^N values of constant voltage generated by said input data converting means to said source electrode to control charge injected into said floating gate during the data write operation

wherein said threshold voltage is determined based on the injected amount of electric charge.

8. A non-volatile memory device capable of storing multi-state data comprising:

input signal converting means for converting a binary input signal into multi-state input data having more than 2 values;

a memory cell for storing input data including a floating gate to and out of which electric charge is injected and subtracted, with a drain electrode, a source electrode and a control gate electrode formed around said floating gate to constitute a memory transistor;

a semiconductor substrate on which said drain electrode and said source electrode are formed;

writing means for writing said multi-state input data to said memory cell as said input data;

reading means for reading the data written in said memory cell; and

output signal converting means for converting the data read by said reading means into a binary output signal;

said input signal converting means including

signal converting means for converting N (a natural number larger than

     1) binary signals into 2^N multi-state data, and

constant voltage generating means for generating 2^N values of predetermined non-zero voltage corresponding to the 2^N multi-state data; and

said writing means including

electric charge injecting means for injecting electric charge into said floating gate, and

controlling means for controlling the amount of electric charge to be injected by said electric charge injecting means including means for applying one of the 2^N values of predetermined non-zero voltage to said source electrode.

9. A non-volatile memory device according to claim 8, wherein said electric charge injecting means comprises:

first voltage applying means for applying zero potential to said control gate electrode and to said semiconductor substrate and for applying positive high voltage to said drain electrode in a data write operation; and

a second voltage application means for applying zero potential to said drain electrode, to said source electrode and to said semiconductor substrate, and for applying positive high voltage to said control electrode in a data erase operation.

10. A non-volatile memory device according to claim 9, wherein said reading means comprises:

fourth voltage applying means for applying 0 potential to said control gate electrode and to said source electrode and for applying prescribed positive voltage to said drain electrode during a data read operation;

detecting means for detecting a current generated between said source electrode and said drain electrode through said semiconductor substrate by said fourth voltage applying means; and

signal generating means for generating an output signal according to the current detected by said detecting means.

11. A non-volatile memory device according to claim 10 wherein said output signal converting means comprises:

voltage generating means for generating M (2^N . . . N;

a natural number larger than

     1) values of voltage corresponding to M values of the detected currents, and

binary signal generating means for generating √

M binary signals corresponding to said M values of voltage produced by said voltage generating means using and to (M-1) values of predetermined voltage.

12. A non-volatile memory device according to claim 8, wherein:

a plurality of said memory cells and said electric charge injecting means are arranged on the non-volatile memory device, and each of said electric charge injecting means is connected to a common voltage source and includes voltage source releasing means for releasing the connection with said common voltage source when the injection of electric charge into each of said floating gates by each of said electric charge injecting means has been stopped.

13. A non-volatile memory device according to claim 12, wherein said source voltage releasing means comprises:

detecting means for detecting a current generated between said source electrode and said drain electrode through said semiconductor substrate when the injection of electric charge into said floating gate electrode in said write operation of data is stopped; and

switching means for cutting off the connection with said common voltage source in response to an output detected by said detecting means.