Nonvolatile semiconductor memory device

• US 5,262,985 A
• Filed: 02/22/1991
• Issued: 11/16/1993
• Est. Priority Date: 02/23/1990
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Wada, Masashi
• Primary Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/659,183
• Time in Patent Office: 998 Days
• Field of Search: 365/185, 365/218, 365/189.01, 365/104
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor

Abstract

A nonvolatile semiconductor memory device according to the present invention comprises a memory cell array composed of a collection of blocks, each block containing memory cells sharing the source or drain, a first region having the memory cell array formed in its surface region, and a control circuit that, in the erase mode, sets the source shared by a plurality of memory cells to be erased in one block at a first potential and the first region at a second potential higher than the GND potential and lower than the first potential, and at the same time, sets the source shared by a plurality of memory cells not to be erased in other blocks at a third potential equal to or higher than the second potential and lower than the first potential.

Claims

1. A nonvolatile semiconductor memory device comprising:

a memory cell array formed in a substrate and including a collection of blocks, each block containing a plurality of memory cells sharing a common terminal, the common terminal being one of a source and a drain;

a first region having a surface region, said plurality of memory cells being formed in said surface region; and

a control circuit that, in an erase mode, sets the common terminal of the plurality of memory cells in a block to be erased at a first potential and sets said first region at a second potential higher than a GND potential and lower than said first potential, and at the same time, sets the common terminal of the plurality of memory cells in a block not to be erased at a third potential equal to or higher than said second potential and lower than said first potential.

2. The nonvolatile semiconductor memory device according to claim 1, wherein said control circuit sets the common terminal of the plurality of memory cells in the clock to be erased at a potential generated by a high voltage generator circuit formed in the substrate.

3. The nonvolatile semiconductor memory device according to claim 1, wherein said control circuit sets said first region at the second potential, the second potential being a power supply potential applied from outside of the substrate.

4. The nonvolatile semiconductor memory device according to claim 1, wherein said control circuit sets the common terminal of the plurality of memory cells in a block not to be erased at a power supply potential supplied from outside of the substrate.

5. The nonvolatile semiconductor memory device according to claim 1, wherein said first region is a well formed in said substrate.

6. The nonvolatile semiconductor memory device according to claim 1, wherein said first region includes an epitaxial layer formed on said substrate and separated into a plurality of wells by grooves, each well corresponding to a block of the collection of blocks.

7. The nonvolatile semiconductor memory device according to claim 1, wherein each memory cell of said plurality of memory cells includes a first insulating film formed on said substrate, a floating gate formed on said first insulating film, a second insulating film formed on said floating gate, and a control gate formed on said second insulating film.

8. The nonvolatile semiconductor memory device according to claim 1, wherein each memory cell of said plurality of memory cells includes a first insulating film formed on said substrate, a floating gate formed on said first insulating film, a second insulating film formed on said floating gate, a control gate formed on said second insulating film, and a select gate separated from side walls of said floating gate and said control gate with a third insulating film and separated from said substrate with a fourth insulating film.

9. The nonvolatile semiconductor memory device according to claim 1, wherein each memory cell of said plurality of memory cells includes a first insulating film formed on said substrate, a floating gate formed on said first insulating film to cover a portion of a channel region, a second insulating film formed on said floating gate, and a control gate formed over a remaining portion of said first insulating film over said channel region not covered with said floating gate, said control gate also being formed on said second insulating film to cover said floating gate.

10. The nonvolatile semiconductor memory device according to claim 1, wherein each memory cell of said plurality of memory cells includes a plurality of memory elements, each memory element of said plurality of memory elements including a first insulating film formed on said substrate, a floating gate formed on said first insulating film, a second insulating film formed on said floating gate, and a control gate formed on said second insulating film, each memory element of said plurality of memory elements being connected in series.

11. A nonvolatile semiconductor memory device comprising:

a memory cell array formed in a substrate and including a collection of blocks, each block containing a plurality of memory cells sharing a common terminal, the common terminal being one of a source and a drain;

a first region having a surface region in which one or more blocks of said collection of blocks are formed; and

a control circuit that, in an erase mode, sets the common terminal of the plurality of memory cells in a block to be erased at a first potential and sets said first region at a second potential higher than a GND potential and lower than said first potential, and at the same time, sets the common terminal of the plurality of memory cells in a block not to be erased at a third potential equal to or higher than said second potential and lower than said first potential.

12. The nonvolatile semiconductor memory device according to claim 11, wherein said control circuit sets the common terminal of the plurality of memory cells in a block to be erased at a potential generated by a high voltage generator circuit formed in the substrate.

13. The nonvolatile semiconductor memory device according to claim 11, wherein said control circuit sets said first region at the second potential, the second potential being a power supply potential applied from outside of the substrate.

14. The nonvolatile semiconductor memory device according to claim 11, wherein said control circuit sets the common terminal of the plurality of memory cells in a block not to be erased at a power supply potential supplied from outside of the substrate.

15. The nonvolatile semiconductor memory device according to claim 11, wherein said first region is a well formed in said substrate.

16. The nonvolatile semiconductor memory device according to claim 11, wherein said first region includes an epitaxial layer formed on said substrate and separated into a plurality of wells by grooves, each well corresponding to a block of the collection of blocks.

17. The nonvolatile semiconductor memory device according to claim 11, wherein each memory cell of said plurality of memory cells includes a first insulating film formed on said substrate, a floating gate formed on said first insulating film, a second insulating film formed on said floating gate, and a control gate formed on said second insulating film.

18. The nonvolatile semiconductor memory device according to claim 11, wherein each memory cell of said plurality of memory cells includes a first insulating film formed on said substrate, a floating gate formed on said first insulating film, a second insulating film formed on said floating gate, a control gate formed on said second insulating film, and a select gate separated from side walls of said floating gate and said control gate with a third insulating film and separated from said substrate with a fourth insulating film.

19. The nonvolatile semiconductor memory device according to claim 11, wherein each memory cell of said plurality of memory cells includes a first insulating film formed on said substrate, a floating gate formed on said first insulating film to cover a portion of a channel region, a second insulating film formed on said floating gate, and a control gate formed over a remaining portion of said first insulating film over said channel region not covered with said floating gate, said control gate also being formed ons aid second insulating film to cover said floating gate.

20. The nonvolatile semiconductor memory device according to claim 11, wherein each memory cell of said plurality of memory cells includes a plurality of memory elements, each memory element of said plurality of memory elements including a first insulating film formed on said substrate, a floating gate formed on said first insulating film, a second insulating film formed on said floating gate, and a control gate formed ons aid second insulating film, each memory element of said plurality of memory elements being connected in series.