Justification decision circuit for an arrangement for bit rate adjustment
First Claim
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1. A circuit for adjusting the bit rate of two plesiochronous signals, comprising:
- memory for storing data of a first signal in parallel in groups of n bits each,means for reading out the data stored in said groups and inserting stuff bits at predetermined locations,a write counter for controlling writing of said data in said memory,a read counter for controlling reading out of said memory, anda justification decision circuit for controlling said means for reading out, said justification decision circuit including a controller and a subtractor, said subtractor having an output which is the difference between the counts of the read and write counters,said subtractor, controller and read counter forming a control loop,characterized in that said controller comprises a mean value determining circuit for determining a mean value of said subtractor output, a track counter, and means for offsetting a magnitude value proportional to said mean value,said mean value determining circuit determining the mean value of the subtractor output over a predetermined time interval,said track counter being arranged for counting modulo n said stuffed bits, and providing a read stop signal for one clock period after each n stuffed bits,said controller further comprising means for stopping said read counter for one block period responsive to said read stop signal, andsaid mean for offsetting using the result of the offset as a preparation signal for incrementing the track counter.
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Abstract
A single signal is formed from two plesiochronous signals. The first signal'"'"'s data are written in parallel in groups of n bits each. Writing and reading are controlled by respective counters, whose counts are also provided to a subtractor. A control loop for bit rate justification is formed by the subtractor, a controller and the read counter. A track counter counts the stuffed bits modulo n, and stops the read counter for one clock period after each n stuffed bits. The mean value of the subtractor output and the count of the track counter are set off against each other, and their result is used for justification formation and a preparation signal for incrementing the track counter.
42 Citations
10 Claims
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1. A circuit for adjusting the bit rate of two plesiochronous signals, comprising:
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memory for storing data of a first signal in parallel in groups of n bits each, means for reading out the data stored in said groups and inserting stuff bits at predetermined locations, a write counter for controlling writing of said data in said memory, a read counter for controlling reading out of said memory, and a justification decision circuit for controlling said means for reading out, said justification decision circuit including a controller and a subtractor, said subtractor having an output which is the difference between the counts of the read and write counters, said subtractor, controller and read counter forming a control loop, characterized in that said controller comprises a mean value determining circuit for determining a mean value of said subtractor output, a track counter, and means for offsetting a magnitude value proportional to said mean value, said mean value determining circuit determining the mean value of the subtractor output over a predetermined time interval, said track counter being arranged for counting modulo n said stuffed bits, and providing a read stop signal for one clock period after each n stuffed bits, said controller further comprising means for stopping said read counter for one block period responsive to said read stop signal, and said mean for offsetting using the result of the offset as a preparation signal for incrementing the track counter. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of adjusting the bit rate of two plesiochronous signals, comprising:
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storing data of a first signal in parallel in groups of n bits each in a memory, counting read bits and reading out the data stored in said groups and inserting stuff bits at predetermined locations according to a read count, counting write clock bits and controlling writing of said data in said memory according to a write count, forming a difference value which is the difference between said read and write counts, and responsive to a function of said difference value, controlling insertion of said stuff bits, characterized by the steps of; determining a mean value of said difference value over a predetermined time interval, counting modulo n the inserted stuff bits to form a track count, and providing a read stop signal for one clock period after each n stuffed bits, determining a magnitude value proportional to said mean value, and offsetting said magnitude value against said track count, stopping said read counter for one clock period responsive to said read stop signal, and using the result of the offset as a preparation signal for incrementing the modulo n count of said stuffed bits. - View Dependent Claims (8, 9, 10)
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Specification
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Current AssigneeLucent Technologies, Inc. (Nokia Corporation)
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Original AssigneeUS Philips Corporation (Koninklijke Philips N.V.)
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InventorsUrbansky, Ralph
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Primary Examiner(s)Kuntz, Curtis
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Assistant Examiner(s)Bocure, Tesfaldet
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Application NumberUS07/751,365Time in Patent Office810 DaysField of Search375/118, 375/112, 370/102, 370/105.1US Class Current375/363CPC Class CodesH04J 3/0623 Synchronous multiplexing sy...
