Circuitry for automatically entering and terminating an initialization mode in a data processing system in response to a control signal

• US 5,263,168 A
• Filed: 06/03/1991
• Issued: 11/16/1993
• Est. Priority Date: 06/03/1991
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Carson, Hubert G. Jr., Toms, Thomas R., Jelemensky, Joseph, Heene, Mark R.
• Primary Examiner(s): Kriess, Kevin A.
• Assistant Examiner(s): Spivak, Kevin
• Application Number:
  US07/709,552
• Time in Patent Office: 897 Days
• Field of Search: 395/425, 395/250, 395/275, 395/200, 395/525, 395/700, 395/650
• US Class Current: 713/1
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

A data processing system (10), comprised of a central processing unit (14) and a memory system (16), has an efficient initialization operation. The memory system (16) provides a bus interface unit (20) to automatically determine whether the system (10) should execute an initialization operation or function in a normal mode of operation. The memory system (16) begins execution of the initialization operation of the system (10) in response to both a logic value of a reset signal and a value of an address transferred by an address bus. The memory system (16) automatically terminates execution of the initialization operation in response to the value of the address transferred by the address bus.

Claims

1. A data processing system, comprising:

a data processor for receiving a plurality of data processing instructions and executing the data processing instructions by selectively generating addresses and receiving data required to implement the execution of the data processing instructions, the data processor having an input for receiving information;

a communication bus coupled to the input of the processor for communicating the data processing instructions, the addresses and data, and a control signal, the control signal enabling the data processing system to operate in an initialization mode;

a memory means for selectively providing the processor with data, a first storage location being addressed during the initialization mode for providing information to the processor, and a second storage location being addressed subsequent to the initialization mode for providing information to the processor; and

a memory control means coupled to the memory means and the communication bus, the memory control means being integrated on a single integrated circuit with the memory means, the memory control means receiving addresses from the data processor, at least one address value selectively addressing one of two storage locations and also receiving the control signal, the at least one address value and the control signal being collectively used to selectively automatically enable the data processing system to operate in the initialization mode, the memory control means automatically terminating operation of the data processing system in the initialization mode in response to a predetermined condition within the data processing system being met.

2. The data processing system of claim 1 wherein the memory control means selectively enables the data processing system to enter the initialization mode in response to both the control signal being asserted and each of the addresses transferred by the communication bus having a value within a predetermined range of address values.

3. The data processing system of claim 1 wherein the memory control means further comprises:

a test means having a first input for receiving a test mode signal provided by a user of the data processing system, the test means providing an enable signal to automatically enter and terminate the initialization mode in response to the test mode signal being asserted.

4. The data processing system of claim 1 wherein the memory control means further comprise:

means coupled to the communication bus for prematurely terminating the initialization mode in response to a stop mode signal provided by a user of the data processing system.

5. The data processing system of claim 1 wherein the memory means may be programmed by a user of the data processing system to selectively provide an initialization mode enable signal to permit the memory control means to selectively prevent the data processing system from entering the initialization mode of operation when the memory control means receives the control signal.

6. The data processing system of claim 1 wherein the memory control means is further comprised of:

a control logic circuit coupled to the communication bus, the control logic circuit receiving the control signal and providing a first initialization signal in response thereto, the first initialization signal enabling the memory control means to access the first storage location of the memory means during the initialization mode of operation;

an address match circuit coupled to the control logic circuit for receiving the first initialization signal, the address match circuit also being coupled to the communication bus for receiving the at least one address value, the address match circuit comparing the at least one address value to determine whether the at least one address value is within a predetermined range of address values and providing a second control signal in response thereto;

a state machine coupled to the address match circuit and the control logic circuit, the state machine receiving the second control signal and enabling the control logic circuit to continue providing the first initialization signal; and

address latch logic means coupled to the control logic circuit, the state machine and the memory means, the address latch logic means providing the at least one address value in a predetermined logic state to the memory means in response to the first initialization signal and the state machine.

7. The data processing system of claim 6 wherein the address latch logic means accesses the first storage location of the memory means when the at least one address value is in the predetermined logic state, and the address latch logic means accesses the second storage location of the memory means when the at least one address value is not in the predetermined logic state.

8. The data processing system of claim 1 wherein the memory means is a flash electrically erasable programmable read only memory (EEPROM), the flash EEPROM being randomly accessible.

9. The data processing system of claim 1 wherein the control signal is a reset signal, the reset signal provided by a user of the data processing system.

10. A data processing system, comprising:

a data processor for receiving a plurality of data processing instructions and executing the data processing instructions by selectively generating addresses and receiving data required to implement the execution of the data processing instructions, the data processor having an input for receiving information;

a communication bus coupled to the input of the processor for communicating the data processing instructions, the addresses and data, and a control signal, the control signal enabling the circuit to operate in an initialization mode;

a memory array for selectively providing the processor with data and initialization mode control information, an initialization mode enable signal being provided to enable the processor to enter the initialization mode in response to receipt of a predetermined address signal, a first storage location being addressed during the initialization mode for providing information to the data processor, and a second storage location being addressed subsequent to the initialization mode for providing information to the data processor; and

a memory interface means coupled to the memory array and the communication bus, the memory interface means being integrated on a single integrated circuit with the memory array, the memory interface means receiving addresses from the data processor, at least one address value selectively addressing one of two storage locations, the memory interface means receiving the initialization mode enable signal from the memory array and also receiving the control signal from the data processor, the at least one address value, the initialization mode enable signal, and the control signal being collectively used to selectively automatically enable the data processing system to enter the initialization mode, the memory interface means automatically terminating the initialization mode in response to a predetermined condition within the data processing system being met.

11. The data processing system of claim 10 wherein the memory interface means further comprises:

a control logic circuit coupled to the communication bus and the memory array, the control logic circuit receiving the control signal from the communication bus and the initialization mode signal from the memory array, and providing a first initialization signal in response thereto, the first initialization signal enabling the memory interface means to access the first storage location of the memory array during the initialization mode of operation;

an address match circuit coupled to the control logic circuit for receiving the first initialization signal, the address match circuit also being coupled to the communication bus for receiving the at least one address value, the address match circuit comparing the at least one address value to determine whether the at least one address value is within a predetermined range of address values and providing a second control signal in response thereto;

a state machine coupled to the address match circuit and the control logic circuit, the state machine receiving the second control signal and enabling the control logic circuit to continue the initialization operation; and

address latch logic means coupled to the control logic circuit, the state machine and the memory array, the address latch logic means providing the at least one address value in a predetermined logic state to the memory array in response to the first initialization signal and the state machine.

12. The data processing system of claim 11 wherein the address latch logic means accesses the first storage location of the memory array when the at least one address value is in the predetermined range of addresses, and the address latch logic means accesses the second storage location of the memory array when the at least one address value is not within the predetermined range of addresses.

13. The a data processing system of claim 10 wherein the memory interface means further comprises:

a test means having a first input for receiving a test mode signal provided by a user of the data processing system, the test means providing an enable signal to automatically enter and terminate the initialization mode in response to the test mode signal being asserted.

14. The data processing of claim 10 wherein the control signal is a reset signal, the reset signal provided by an external user.

15. A data processing system, comprising:

a data processor for receiving a plurality of data processing instructions and executing the data processing instructions by selectively generating addresses and receiving data required to implement the execution of the data processing instructions, the data processor having an input for receiving information;

a communication bus coupled to the input of the processor for communicating the data processing instructions, the addresses and data, and a control signal, the control signal enabling the data processing system to operate in an initialization mode;

a memory means for selectively providing the processor with data, a first storage location being addressed during the initialization mode for providing information to the processor, and a second storage location being addressed subsequent to the initialization mode for providing information to the processor; and

a memory control means coupled to the memory means and the communication bus, the memory control means being integrated on a single integrated circuit with the memory means, the memory control means receiving addresses from the data processor, at least one address value selectively addressing one of two storage locations and also receiving the control signal, the at least one address value and the control signal being collectively used to selectively automatically enable the data processing system to operate in the initialization mode, the memory control means automatically terminating operation of the data processing system in the initialization mode in response to a predetermined condition within the data processing system being met, wherein the memory control means comprises;

a control logic circuit coupled to the communication bus, the control logic circuit receiving the control signal and providing a first initialization signal in response thereto, the first initialization signal enabling the memory control means to access the first storage location of the memory means during the initialization mode of operation;

an address match circuit coupled to the control logic circuit for receiving the first initialization signal, the address match circuit also being coupled to the communication bus for receiving the at least one address value, the address match circuit comparing the at least one address value to determine whether the at least one address value is within a predetermined range of address values and providing a second control signal in response thereto;

a state machine coupled to the address match circuit and the control logic circuit, the state machine receiving the second control signal and enabling the control logic circuit to continue providing the first initialization signal; and

address latch logic means coupled to the control logic circuit, the state machine and the memory means, the address latch logic means providing the at least one address value in a predetermined logic state to the memory means in response to the first initialization signal and the state machine.

16. A data processing system, comprising:

a data processor for receiving a plurality of data processing instructions and executing the data processing instructions by selectively generating addresses and receiving data required to implement the execution of the data processing instructions, the data processor having an input for receiving information;

a communication bus coupled to the input of the processor for communicating the data processing instructions, the addresses and data, and a control signal, the control signal enabling the circuit to operate in an initialization mode;

a memory array for selectively providing the processor with data and initialization mode control information, an initialization mode enable signal being provided to enable the processor to enter the initialization mode in response to receipt of a predetermined address signal, a first storage location being addressed during the initialization mode for providing information to the data processor, and a second storage location being addressed subsequent to the initialization mode for providing information to the data processor;

a control logic circuit coupled to the communication bus and the memory array, the control logic circuit receiving the control signal from the communication bus and the initialization mode signal from the memory array, and providing a first initialization signal in response thereto, the first initialization signal enabling the memory interface means to access the first storage location of the memory array during the initialization mode of operation;

an address match circuit coupled to the control logic circuit for receiving the first initialization signal, the address match circuit also being coupled to the communication bus for receiving the at least one address value, the address match circuit comparing the at least one address value to determine whether the at least one address value is within a predetermined range of address values and providing a second control signal in response thereto;

a state machine coupled to the address match circuit and the control logic circuit, the state machine receiving the second control signal and enabling the control logic circuit to continue the initialization operation; and

address latch logic means coupled to the control logic circuit, the state machine and the memory array, the address latch logic means providing the at least one address value in a predetermined logic state to the memory array in response to the first initialization signal and the state machine.

17. A method for initializing a data processing system, wherein the data processing system performs the steps of:

providing a first initialization signal to a data processing system;

providing an address value to a memory array in the data processing system, the address value selectively addressing one of two storage locations in a memory array;

determining whether the address value is in a predetermined range of addresses;

asserting a first control signal to indicate that the address value is in the predetermined range of addresses and negating the first control signal to indicate that the address value is not within the predetermined range of addresses;

selectively modifying the address value in response to a value of the first control signal and the first initialization signal to provide a modified address value;

using the modified address value to access a first one of the two storage locations in the memory array when the first initialization signal is asserted; and

using the modified address value to access a second one of the two storage locations in the memory array when the first initialization signal is asserted.

18. The method of claim 17, wherein the data processing system performs the step of:

programming the memory array to provide an initialization mode enable signal to selectively enable the data processing system to enter an initialization mode of operation; and

selectively asserting the initialization mode enable signal in response to a logic state of the first control signal.