Procedure for arranging switch-type control in a radio telephone

• US 5,263,178 A
• Filed: 10/03/1991
• Issued: 11/16/1993
• Est. Priority Date: 10/05/1990
• Status: Expired due to Term

• Current Assignee: Nokia Solutions and Networks US LLC (Nokia Corporation)
• Original Assignee: Nokia Mobile Phones OY (Nokia Corporation)
• Inventors: Liukkonen, Jorma
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): KEOUGH, TIMOTHY
• Application Number:
  US07/770,879
• Time in Patent Office: 775 Days
• Field of Search: 307/520, 307/521, 307/522, 307/262, 328/167, 328/155, 455/75, 455/76, 455/161.1, 455/161.2, 455/165.1, 455/180.3, 455/183.1, 455/183.2, 455/260
• US Class Current: 455/76
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04B 1/16 Circuits

Abstract

The radio unit of a modern radio telephone comprises a plurality of controlled two-position switches. Each controlled switch most often requires an individual control line from a processor. The greater the number of controlled switches in the circuit, the more control lines that are needed. The number of control lines is substantially reduced in that from one or several control lines of a frequency synthesizer in the radio unit, a switch line is branched off for the controlled switches. During the time in which the synthesizer circuit receives no control signals, the logic unit of the radio telephone supplies a control voltage to the controlled switches over a control line of the synthesizer and over a switch line branched therefrom.

Claims

1. A method for controlling a frequency synthesizer circuit and switches for a radio unit of a radio telephone having a logic unit, comprising the steps of:

providing frequency synthesizer circuit means connected to said logic unit of said radio telephone by a plurality of first control lines, said frequency synthesizer circuit means including a phase-locked loop;

providing at least one said radio unit switches with a connection to said logic unit, said connection including at least one second control line connected at one end to said at least one switch and at the other end to a selected one of said first control lines at a position intermediate said logic unit and said synthesizer circuit means;

outputting first control signals from said logic unit onto said first control lines during a first time period to select performance of said synthesizer circuit means; and

outputting second control signals from said logic unit onto said first control lines, and via said connection onto said at least one second control line, during a second time period to control an operating state of said at least one switch.

2. A method as in claim 1, further comprising the step:

providing low pass filter means in said at least one second control line to inhibit said first control signals from affecting the operating state of said at least one switch.

3. A method as in claim 2, further comprising the step of providing enable signals to said synthesizer circuit means from said logic unit during said first time period via a selected one of said first control lines, signals on the remaining first control lines being entered in said synthesizer circuit means in response to said enable signal, said selected first control line being independent of said at least one switch.

4. A method as in claim 1, further comprising the step of providing enable signals to said synthesizer circuit means from said logic unit during said first time period via a selected one of said first control lines, signals on the remaining first control lines being entered in said synthesizer circuit means in response to said enable signal, said selected first control line being independent of said at least one switch.

5. A control circuit arrangement in a radio telephone, comprising:

a logic unit for providing first control signals during a first time period, and second control signals during a second time period;

a frequency synthesizer means including a phase-locked loop, performance of said frequency synthesizer means being set by input of said first control signals from said logic unit;

a plurality of first control lines connected between said logic unit and said frequency synthesizer means for carrying said first control signals from said logic unit to said frequency synthesizer means;

at least one control switch requiring a second control signal to set the operating state of said switch;

at least one second control line connected respectively between said at least one switch and a connection to a first control line, said connection being between said frequency synthesizer means and said logic unit, said second control signals being provided to said at least one switch during said second time period when said synthesizer means receives no first control signals.

6. A circuit arrangement as in claim 5, further comprising low pass filter means in said at least one second control line to inhibit said first control signals from affecting the operating state of said at least one switch.

7. A circuit arrangement as in claim 6, wherein one of said first control signals provides an enable pulse to said frequency synthesizer means via a selected first control line, said enable pulse causing said first control signals to enter into said frequency synthesizer means, said selected first control line being independent of said at least one switch and its associated second control line.

8. A circuit arrangement as in claim 5, wherein one of said first control signals provides an enable pulse to said frequency synthesizer means via a selected first control line, said enable pulse causing said first control signals to enter into said frequency synthesizer means, said selected first control line being independent of said at least one switch and its associated second control line.