Integrated circuit electromigration monitor

• US 5,264,377 A
• Filed: 04/03/1992
• Issued: 11/23/1993
• Est. Priority Date: 03/21/1990
• Status: Expired due to Term

• Current Assignee: AT&T, Inc.
• Original Assignee: AT&T, Inc.
• Inventors: Chesire, Daniel P., Oates, Anthony S.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): OJAN, OURMAZD
• Application Number:
  US07/864,207
• Time in Patent Office: 599 Days
• Field of Search: 437/8, 437/170, 437/957
• US Class Current: 438/11
• CPC Class Codes: G01R 31/2642 Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
• CPC Class Codes: G01R 31/2858 Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

The electromigration characteristics of integrated circuit conductors are determined by passing a high current for a short period of time through an inventive test structure. This provides a rapid test in a more accurate manner than with the prior art SWEAT (Standard Wafer-level Electromigration Accelerated Test) structure. The test results have been found to be well correlated with long-term low current electromigration tests. A sensitive differential test may be implemented that determines the effects of topography features. The inventive test technique can be performed on every wafer lot, or even every wafer, so that adjustments to the wafer fabrication process can be rapidly implemented.

Claims

1. A method of making an integrated circuit including the step of determining the electromigration characteristics of an integrated circuit conductor by steps comprising flowing an electrical current through a test structure, and determining the time for a failure to occur,

characterized in that the current density of said electrical current is at least 5×

10⁶ amps/cm², and said test structure comprises an elongated test conductor at least 50 micrometers long, wherein said elongated test conductor is contacted at its ends by wider metal conductors having a width at least 5 times the width of said elongated test conductor, and with said wider metal conductors tapering down to the width of said test conductor.

2. The method of claim 1 wherein the width of the wider metal conductors is about 10 times the width of said elongated test conductor.

3. The method of claim 1 wherein the current density of said electrical current is at least 1×

10⁷ amps/cm².

4. The method of claim 1 wherein said test conductor is about 800 micrometers long.

5. The method of claim 1 wherein said test structure further comprises voltage tap conductors that connect to each of said wider metal conductors at the point at which said wider metal conductors taper down to the width of said test conductor.

6. The method of claim 1 wherein said test structure further comprises elongated side conductors located on both sides of said test conductor and contacted by a bondpad.

7. The method of claim 1 wherein said test structure further comprises elongated topographic features located under, and oriented generally transverse to, said test conductor, wherein said elongated topographic features are formed of conductive material that is insulated from said test conductor.

8. The method of claim 1 further comprising the step of adjusting a parameter of a process step used in making said integrated circuit in response to information derived from said determining the electromigration characteristics of an integrated circuit conductor.

9. The method of claim 7 wherein said process step is a dielectric deposition process.

10. The method of claim 8 wherein said parameter is the thickness of said dielectric.

11. The method of claim 7 wherein said process step is a conductor forming process step.

12. The method of claim 10 wherein said conductor forming process step is a conductor deposition step.

13. The method of claim 10 wherein said conductor forming process step is a conductor etching step.

14. The method of claim 10 wherein said parameter is the thickness of said conductor.

15. The method of claim 10 wherein said parameter is the width of said conductor.

16. The method of claim 10 wherein said parameter is the composition of said conductor.

17. A method of making an integrated circuit including the step of determining the electromigration characteristics of an integrated circuit conductor,

characterized by steps comprising flowing electrical current through first and second test structures, and comparing the effect of the current flow on the structures, wherein said first test structure comprises elongated topographic features located under, and oriented generally transverse to, said test conductor, and said second test structure is located on a generally planar surface, and further

characterized in that each of said test structures comprise elongated test conductors at least 50 micrometers long, wherein said elongated test conductors are contacted at their ends by wider metal conductors having a width at least 5 times the width of said elongated test conductors, and with said wider metal conductors tapering down to the width of said test conductors.

18. The method of claim 17 wherein the current density of said electrical current is at least 5×

10⁶ amps/cm².

19. The method of claim 18 wherein said elongated topographic features are formed of conductive material that is insulated from said test conductor.

20. The method of claim 18 wherein said comparing includes comparing the resistance of the test conductor of said first test structure to the resistance of the test conductor of said second test structure during said flowing electrical current.

21. The method of claim 18 wherein said comparing includes comparing the time of failure of the test conductor of said first test structure to the time of failure of the test conductor of said second test structure.

22. A method of making an integrated circuit including the step of determining the electromigration characteristics of an integrated circuit conductor,

characterized by steps comprising flowing electrical current through an elongated test conductor at least 50 micrometers long, wherein said elongated test conductor is contacted at both ends by wider metal conductors having a width at least 5 times the width of said elongated test conductor, and with said wider metal conductors tapering down to the width of said test conductor.

23. The method of claim 22 wherein said elongated test conductor is about 800 micrometers long.

24. The method of claim 23 wherein elongated topographic features are located under, and generally transverse to, said test conductor.

25. The method of claim 24 wherein said elongated topographic features are formed of conductive material that is insulated from said test conductor.

26. The method of claim 22 wherein the width of said wider metal conductors is approximately 10 times the width of said elongated test conductor.

27. The method of claim 22 further comprising the step of measuring the voltage between voltage tap conductors that connect to each of said wider metal conductors at the point at which said wider metal conductors taper down to the width of said test conductor.

28. The method of claim 22 wherein said elongated test conductor has a width of less than 10 micrometers.