Diffused buried plate trench dram cell array

• US 5,264,716 A
• Filed: 01/09/1992
• Issued: 11/23/1993
• Est. Priority Date: 01/09/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kenney, Donald M.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/819,148
• Time in Patent Office: 684 Days
• Field of Search: 257/296, 257/301, 257/304, 257/311, 257/390, 257/544, 257/532, 257/379, 361/313, 437/52
• US Class Current: 257/301
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

A high density substrate plate DRAM cell memory device is described in which a buried plate region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The buried region is partially formed by lateral outdiffusion from the sidewalls of the deep trenches and partially formed by an N-well surface diffusion which entirely surrounds the DRAM array region.

Claims

1. A dynamic random access memory device comprising:

a semiconductor substrate having a first region of a first conductivity type;

at least one array of dynamic memory cells, each cell comprising an access transistor coupled to a storage capacitor, the transistor of each memory cell being formed within a second region of said semiconductor substrate, each access transistor having a control electrode, a data line contact region, a storage node region, and a channel region;

a plurality of signal storage capacitors formed in a plurality of trenches in said substrate, each capacitor including a signal storage node region and a reference voltage node region separated by a dielectric insulator, the reference voltage node region being formed on said first region of said substrate and the signal storage node region of each capacitor being connected to a corresponding storage node region of one of said access transistors;

means for physically and electrically isolating all of the channel regions of said access transistors within said one array from said first region of said substrate, said isolating means comprising a third region of opposite conductivity type to said first region, said third region formed laterally between said first and second regions, said third region intersecting and extending below the bottom of all of said trenches;

said third region comprising said reference voltage node region having a substantially constant impurity doping concentration throughout its depth and said third region comprising an isolation region extending substantially around said array and extending between said reference voltage node region and a surface of said semiconductor substrate; and

means for biasing said first, second and third regions of said substrate to first, second and third different reference voltages.

2. The dynamic random access memory device of claim 1 wherein the reference voltage node region of said third region has an impurity doping level which exceeds that of the first region of said substrate.

3. The dynamic random access memory device of claim 2 wherein the impurity type of said first region is P-type.

4. The dynamic random access memory device of claim 3 wherein the dopant impurity of said first region is boron and the dopant impurity in the reference voltage node region is arsenic.

5. The dynamic random access memory device of claim 4 wherein the access transistors are N-channel FET devices.

6. A dynamic random access memory device comprising:

a plurality of deep trenches arranged in a rectangular matrix on the surface of a semiconductor substrate, the spacing between adjacent trenches being substantially equal in both a lateral and transverse direction;

a buried plate diffused region being associated with all of said deep trenches;

each of a first plurality of said deep trenches being associated with a substrate plate trench DRAM cell including a transfer device, a data node and a storage node connected to a capacitor plate formed within a deep trench and coupled to a region of the substrate within the buried plate diffused region;

each of a second plurality of said deep trenches being contacting with a surface diffused isolation region enclosing the perimeter of the first plurality of said deep trenches and contacting the buried plate diffused region so that the substrate region within the matrix is electrically and physically isolated from the remainder of the substrate.

7. The dynamic random access memory device of claim 6 wherein the buried plate diffused region has a dopant impurity profile which is substantially constant throughout the depth of said buried plate diffused region.

8. The dynamic random access memory device of claim 7 wherein the impurity conductivity type of the substrate is P-type and the impurity conductivity type of the buried plate diffused region and the surface diffused isolation region is N-type.

9. The dynamic random access memory device of claim 8 wherein the impurity in the buried plate diffused region is arsenic.