High density SRAM circuit with single-ended memory cells

• US 5,265,047 A
• Filed: 03/09/1992
• Issued: 11/23/1993
• Est. Priority Date: 03/09/1992
• Status: Expired due to Fees

• Current Assignee: Monolithic System Technology
• Original Assignee: Monolithic System Technology
• Inventors: Leung, Wingyu, Hsu, Fu-Chieh
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): DINH, SON T
• Application Number:
  US07/848,551
• Time in Patent Office: 624 Days
• Field of Search: 365/154, 365/156, 307/238, 307/279
• US Class Current: 365/154
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/067 Single-ended amplifiers

Abstract

A high density, static random access memory (SRAM) circuit with single-ended memory cells employs a plurality of (4T-2R) or (6T) type SRAM cells and a regenerative sense amplifier. Each of the SRAM cells employs a single bit-line (BL) and two word lines.

Claims

1. A static, random access memory cell comprising:

a bit line;

a first word line;

a second word line;

a first resistor;

a second resistor;

a first transistor having a gate connected to said first word line and a channel having a first end connected to said bit line and a second end coupled by said first resistor to a power supply potential;

a second transistor having a gate connected to said second word line and a channel having a first end connected to the power supply potential and a second end coupled by said second resistor to the power supply potential;

a third transistor having a gate connected to said second transistor channel second end and a channel connected between the said first transistor channel second end and a circuit ground potential;

a fourth transistor having a gate connected to said first transistor channel second end and a channel connected between said second transistor channel second end and the circuit ground potential.

2. A static, random access memory circuit as recited in Claim 1, further comprising:

regenerative sense amplifier including;

a regenerative sense amplifier first line;

a regenerative sense amplifier second line;

an internal node;

a first transistor having a gate connected to said internal node and a channel connected between said bit line and said regenerative sense amplifier second line;

a second transistor having a gate connected to said bit line and a channel connected between said internal node and said regenerative sense amplifier second line;

a third transistor having a gate connected to said internal node and a channel connected between said regenerative sense amplifier first line and said bit line; and

a fourth transistor having a gate connected said bit line and a channel connected between said regenerative sense amplifier first line and said internal node.

3. A static, random access memory circuit as recited in claim 2, wherein said regenerative sense amplifier further includes:

a first sense amplifier selecting line;

a second sense amplifier selecting line;

a fifth transistor having a gate connected to said regenerative sense amplifier first sense amplifier selecting line and a channel connected between said regenerative sense amplifier first line and the power supply potential; and

a sixth transistor having a gate connected to said regenerative sense amplifier second sense amplifier selecting line and a channel connected between said regenerative sense amplifier second line and the circuit ground potential.

4. A static, random access memory circuit as recited in claim 1 wherein said memory cell first, second, third, and fourth transistors each have a channel width which is approximately fifty percent of a predetermined width.

5. A static, random access memory circuit as recited in claim 2 further comprising a bit line equalization circuit including:

an equalization control line;

a voltage reference line;

a first transistor having a gate connected to said equalization control line and a channel connected to said memory cell bit line and said internal node; and

a second transistor having a gate connected to said equalization control line and a channel connected to said internal node and said voltage reference line.

6. A static, random access memory circuit as recited in claim 2 further comprising a dummy cell circuit including:

a dummy word line;

a first transistor having a gate connected to said dummy word line and a channel having a first end connected to said internal node and a second end; and

a second transistor having a gate connected to the power supply potential and a channel connected to said dummy cell first transistor channel second end and the circuit ground potential.

7. A static, random access memory cell comprising:

a bit line;

a first word line;

a second word line;

a first transistor having a gate connected to said first word line and a channel having a first end connected to said bit line and a second end;

a second transistor having a gate connected to said second word line and a channel having a first end connected to the power supply potential and a second end;

a third transistor having a gate connected to said second transistor channel second end and a channel connected between the said first transistor channel second end and a circuit ground potential; and

a fourth transistor having a gate connected to said first transistor channel second end and a channel connected between said second transistor channel second end and the circuit ground potential;

a fifth transistor having a gate connected to said second transistor channel second end and a channel connected from said first transistor channel second end to a power supply potential; and

a sixth transistor having a gate connected to said first transistor channel second end and a channel connected from said second transistor channel second end to the power supply potential.

8. A static, random access memory circuit as recited in claim 7, further comprising a regenerative sense amplifier including:

a regenerative sense amplifier first line;

a regenerative sense amplifier second line;

an internal node;

a first transistor having a gate connected to said internal node and a channel connected between said memory cell bit line and said regenerative sense amplifier second line;

a second transistor having a gate connected to said memory cell bit line and a channel connected between said internal node and said regenerative sense amplifier second line;

a third transistor having a gate connected to said internal node and a channel connected between said regenerative sense amplifier first line and said memory cell bit line; and

a fourth transistor having a gate connected said memory cell bit line and a channel connected between said regenerative sense amplifier first line and said internal node.

9. A static, random access memory circuit as recited in claim 8 wherein said regenerative sense amplifier further includes:

a first sense amplifier selecting line;

a second sense amplifier selecting line;

a fifth transistor having a gate connected to said regenerative sense amplifier first sense amplifier selecting line and a channel connected between said regenerative sense amplifier first line and the power supply potential; and

a sixth transistor having a gate connected to said regenerative sense amplifier second sense amplifier selecting line and a channel connected between said regenerative sense amplifier second line and the circuit ground potential.

10. A static, random access memory circuit as recited in claim 7 wherein said memory cell first, second, third, and fourth transistors each have a channel width which is within fifty percent of a predetermined width.

11. A static, random access memory circuit as recited in claim 8 further comprising a bit line equalization circuit including:

an equalization control line;

a voltage reference line;

a first transistor having a gate connected to said equalization control line and a channel connected to said memory cell bit line and said internal node; and

a second transistor having a gate connected to said equalization control line and a channel connected to said internal node and said voltage reference line.

12. A static, random access memory circuit as recited in claim 8 further comprising a dummy cell circuit including:

a dummy word line;

a first transistor having a gate connected to said dummy word line and a channel having a first end connected to said internal node; and

a second transistor having a gate connected to the power supply potential and a channel connected to said dummy cell first transistor channel second end and the circuit ground potential.

13. A static random access memory cell comprising:

a bit line;

a first source of control signals;

a second source of control signals;

a first load having a first end connected to a reference potential;

a second load having a first end connected to the reference potential;

a first transistor connecting the second end of the first load to ground;

a second transistor connecting the second end of the second load to ground;

a first transfer switch connected between the bit line and a gate of the second transistor and controlled by the control signals from the first source; and

a second transfer switch connected between the reference potential and a gate of the first transistor and controlled by the control signals from the second source;

wherein a second end of the first load is connected to the gate of the second transistor, and a second end of the second load is connected to the gate of the first transistor.