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Refresh control arrangement and a method for refreshing a plurality of random access memory banks in a memory system

  • US 5,265,231 A
  • Filed: 02/08/1991
  • Issued: 11/23/1993
  • Est. Priority Date: 02/08/1991
  • Status: Expired due to Fees
First Claim
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1. A memory controller for controlling a memory including a plurality of memory banks, each memory bank including a plurality of storage locations, said memory controller receiving memory access requests over a bus in a digital computer system for initiating a memory access operation in connection with a storage location in a selected bank, said memory controller comprising:

  • A. a memory access control circuit for (i) receiving memory access requests over the bus and for performing a memory access operation in connection with a storage location in response thereto and (ii) initiating a refresh operation with respect to selected ones of said memory banks;

    B. a memory refresh control circuit comprising;

    i. a refresh timer for generating a refresh timing signal to indicate an end of each of a succession of predetermined refresh time intervals;

    ii. a concurrent refresh control circuit connected to said refresh timer and said memory access control circuit for enabling said memory access control circuit to initiate a refresh operation in connection with a selected memory bank following the generation of the refresh timing signal concurrent with the performance by said memory access control circuit of a memory access operation, said concurrent refresh control circuit initiating a refresh operation in connection with a memory bank other than a memory bank with which the memory access control means is performing a memory access operation, said concurrent refresh control circuit maintaining concurrent refresh status information indicating refresh status of each said memory bank; and

    iii. an urgent refresh control circuit connected to said refresh timer, said memory access control circuit and said concurrent refresh control circuit for enabling said memory access control circuit to initiate a refresh operation in response to generation of the refresh timing signal and the concurrent refresh status information maintained by said concurrent refresh control circuit, in connection with a plurality of memory banks with respect to which said concurrent refresh control circuit did not initiate a refresh operation during the preceding timing interval and for concurrently disabling said memory access control means from performing a memory access operation.

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