Refresh control arrangement and a method for refreshing a plurality of random access memory banks in a memory system

• US 5,265,231 A
• Filed: 02/08/1991
• Issued: 11/23/1993
• Est. Priority Date: 02/08/1991
• Status: Expired due to Fees

• Current Assignee: TM Patents LP
• Original Assignee: Thinking Machines Corporation (Oracle Corporation)
• Inventors: Nuwayser, Sami H.
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): Nguyen, Hiep T.
• Application Number:
  US07/652,801
• Time in Patent Office: 1,019 Days
• Field of Search: 395/425, 395/400, 364/200 MS File, 364/900 MS File, 365/222, 365/230.03
• US Class Current: 711/106
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory controller and a method for controlling a memory including at least one memory bank including a plurality of storage locations. The memory controller receives memory access requests over a bus in a digital computer system and, in response initiates a memory access operation in connection with a storage location. The memory controller comprises a memory access control circuit that receives memory access requests over the bus and for performing a memory access operation in connection with a storage location in response thereto. A memory refresh control circuit includes a yellow refresh control circuit and a red refresh control circuit, both of which control refresh of the memory bank(s). The yellow refresh control circuit initiates a refresh operation in connection with a memory bank while the memory access control circuit is performing a memory access operation. In that connection, the yellow refresh control circuit initiates a refresh operation in connection with a memory bank other than the bank with respect to which the memory access control circuit is performing a memory access operation. The red refresh control circuit, on the other hand, initiates a refresh operation in connection with at least one memory bank and concurrently disables said memory access control circuit from performing a memory access operation.

Claims

1. A memory controller for controlling a memory including a plurality of memory banks, each memory bank including a plurality of storage locations, said memory controller receiving memory access requests over a bus in a digital computer system for initiating a memory access operation in connection with a storage location in a selected bank, said memory controller comprising:

A. a memory access control circuit for (i) receiving memory access requests over the bus and for performing a memory access operation in connection with a storage location in response thereto and (ii) initiating a refresh operation with respect to selected ones of said memory banks;

B. a memory refresh control circuit comprising;

i. a refresh timer for generating a refresh timing signal to indicate an end of each of a succession of predetermined refresh time intervals;

ii. a concurrent refresh control circuit connected to said refresh timer and said memory access control circuit for enabling said memory access control circuit to initiate a refresh operation in connection with a selected memory bank following the generation of the refresh timing signal concurrent with the performance by said memory access control circuit of a memory access operation, said concurrent refresh control circuit initiating a refresh operation in connection with a memory bank other than a memory bank with which the memory access control means is performing a memory access operation, said concurrent refresh control circuit maintaining concurrent refresh status information indicating refresh status of each said memory bank; and

iii. an urgent refresh control circuit connected to said refresh timer, said memory access control circuit and said concurrent refresh control circuit for enabling said memory access control circuit to initiate a refresh operation in response to generation of the refresh timing signal and the concurrent refresh status information maintained by said concurrent refresh control circuit, in connection with a plurality of memory banks with respect to which said concurrent refresh control circuit did not initiate a refresh operation during the preceding timing interval and for concurrently disabling said memory access control means from performing a memory access operation.

2. A memory controller as recited in claim 1 further comprising a memory bank control signal generating circuit for generating memory bank control signals for controlling said memory banks during a memory operation and a refresh operation,

A. said memory access control circuit generating a signal identifying a memory bank with which it is performing a memory access operation;

B. said concurrent refresh control circuit includes;

i. a concurrent refresh status circuit for generating concurrent refresh status indications for said memory banks in response to generation of said timing signal; and

ii. a concurrent refresh priority circuit for selecting a memory bank with which to initiate a refresh operation in response to the concurrent refresh status indications generated by said concurrent refresh status circuit for said memory banks and the memory bank identified by the signal from said memory access control circuit to thereby identify a memory bank with which a refresh operation is to be performed, said memory bank control signal generating circuit generating memory bank control signals to enable a refresh operation with respect to the identified memory bank.

3. A memory controller as recited in claim 2 in which said concurrent refresh status circuit comprises:

A. a concurrent refresh status flag bank including a plurality of concurrent refresh flags each associated with a memory bank, each concurrent refresh flag having a condition;

B. a concurrent refresh status flag conditioning circuit for establishing the condition of said concurrent refresh flags in response to the refresh timing signal, thereby to identify ones of said memory banks with respect to which a concurrent refresh operation is to take place.

4. A memory controller as recited in claim 3 in which said memory controller generates a plurality of memory bank present signals each having a condition indicating the presence or absence of a memory bank, said concurrent refresh status flag conditioning circuit establishing the condition of each said concurrent refresh flag in response to the condition of the corresponding memory bank present signal and the refresh timing signal.

5. A memory controller as defined in claim 4 in which said concurrent refresh priority circuit generates a concurrent refresh bank grant signal to identify a memory bank to be refreshed, said concurrent refresh status flag conditioning circuit further conditioning the concurrent refresh flags in response to said concurrent refresh bank grant signal.

6. A memory controller as defined in claim 3 in which (i) said memory controller generates a plurality of memory bank present signals each having a condition indicating the presence or absence of a memory bank, (ii) said concurrent refresh priority circuit generates a concurrent refresh bank grant signal to identify a memory bank to be refreshed, and (iii) said concurrent refresh flags each have a set condition to indicate that a concurrent condition is to take place and a reset condition, said concurrent refresh status circuit comprises:

A. a concurrent refresh set condition enabling circuit for generating a plurality of concurrent refresh set condition enabling signals each associated with a memory bank and corresponding to the condition of the memory bank present signal of the corresponding memory bank in response to said refresh timing signal;

B. a concurrent refresh reset condition enabling circuit responsive to said concurrent refresh grant signal to generate a plurality of concurrent refresh reset enabling signals each associated with a corresponding memory bank and

C. a concurrent refresh condition composite enabling circuit for generating a plurality of concurrent refresh condition control signals, each for controlling the conditioning one of said concurrent refresh flags, each of said concurrent refresh condition control signals being generated in response to the concurrent refresh set condition enabling signal in the absence of the concurrent refresh reset enabling signal associated with the corresponding memory bank.

7. A memory controller as defined in claim 2 in which said urgent refresh control circuit includes:

A. an urgent refresh status circuit for generating urgent refresh status indications for said memory banks in response to generation of said timing signal and the concurrent refresh status indications generated by said concurrent refresh status circuit; and

B. an urgent refresh priority circuit for selecting a memory bank with which to initiate a refresh operation in response to the urgent refresh status indications generated by said urgent refresh status circuit for said memory banks, said memory bank control signal generating circuit generating memory bank control signals to enable a refresh operation with respect to the identified memory bank.

8. A memory controller as recited in claim 7 in which said urgent refresh status circuit comprises:

A. an urgent refresh status flag bank including a plurality of urgent refresh flags each associated with a memory bank, each urgent refresh flag having a condition;

B. an urgent refresh status flag conditioning circuit for establishing the condition of said urgent refresh flags in response to the refresh timing signal, thereby to identify ones of said memory banks with respect to which an urgent refresh operation is to take place.

9. A memory controller as recited in claim 8 in which said memory controller generates a plurality of memory bank present signals each having a condition indicating the presence of a memory bank, said urgent refresh status flag conditioning circuit establishing the condition of each said urgent refresh flag in response to the condition of the corresponding memory bank present signal, the refresh timing signal, and the condition of the concurrent refresh flag associated with the corresponding memory bank.

10. A memory controller as defined in claim 9 in which said urgent refresh priority circuit generates an urgent refresh bank grant signal to identify a memory bank to be refreshed, said urgent refresh status flag conditioning circuit further conditioning the urgent refresh flags in response to said urgent refresh bank grant signal.

11. A memory controller as defined in claim 8 in which (i) said memory controller generates a plurality of memory bank present signals each having a condition indicating the presence of a memory bank, (ii) said urgent refresh priority circuit generates an urgent refresh bank grant signal to identify a memory bank to be refreshed, and (iii) said urgent refresh flags each have a set condition to indicate that an urgent condition is to take place and a reset condition, said urgent refresh status circuit comprises:

A. an urgent refresh set condition enabling circuit for generating a plurality of urgent refresh set condition enabling signals each associated with a memory bank and corresponding to the condition of the memory bank present signal of the corresponding memory bank in response to said refresh timing signal and the condition of the concurrent refresh flag of the associated memory bank;

B. an urgent refresh reset condition enabling circuit responsive to said urgent refresh grant signal to generate a plurality of urgent refresh reset enabling signals each associated with a corresponding memory bank and

C. an urgent refresh condition composite enabling circuit for generating a plurality of composite urgent refresh condition enabling signals, each for conditioning one of said urgent refresh flags, each of said composite urgent refresh condition enabling signals being generated response to the urgent refresh set condition enabling signal and the urgent refresh reset enabling signal associated with the corresponding memory bank.

12. A method for operating a memory controller for controlling a memory including a plurality of memory banks, each memory bank including a plurality of storage locations, said memory controller receiving memory access requests over a bus in a digital computer system for initiating a memory access operation in connection with a storage location in a selected bank, said method comprising the steps of:

A. receiving memory access requests over the bus and performing a memory access operation in connection with a storage location in response thereto;

B. generating a timing signal to indicate an end of each of a succession of predetermined time intervals;

C. initiating a concurrent refresh operation in connection with a selected memory bank following the generation of the timing signal concurrent with the performance of a memory access operation, the concurrent refresh operation being initiated in connection with a memory bank other than a memory bank with which the memory access operation is being performed, and maintaining concurrent refresh status information indicating refresh status of each said memory bank; and

D. determining in response to a timing signal and the concurrent refresh status information the refresh status of each said memory bank and initiating an urgent refresh operation in response to generation of the timing signal in connection with a memory bank which was not refreshed by concurrent refresh operations during the preceding timing interval, and disabling said memory access operations during a said urgent refresh operation.