Fabricating dual gate thin film transistors

• US 5,266,515 A
• Filed: 03/02/1992
• Issued: 11/30/1993
• Est. Priority Date: 03/02/1992
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Robb, Stephen P., Robb, Francine Y.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Pham, Long
• Application Number:
  US07/844,077
• Time in Patent Office: 638 Days
• Field of Search: 437/56, 257/67, 257/69, 257/337, 257/338
• US Class Current: 438/154
• CPC Class Codes: H01L 21/8236 Combination of enhancement and depletion transistors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: Y10S 148/126 Power FETs

Abstract

A method for fabricating a dual gate thin film transistor using a power MOSFET process having a first gate area (22) made from a monocrystalline silicon. A dielectric layer (25) is formed over the monocrystalline silicon. A first gate electrode (58) contacts the first gate area (22). A thin film transistor is fabricated on a first island of polysilicon (29) over the dielectric layer (25). The thin film transistor has a second gate electrode (55), and drain and source electrodes (56, 57) wherein the drain and source electrodes (56, 57) contact different portions of the first island of polysilicon (29). Preferably, the first gate electrode (58) is coupled to the second gate electrode (55).

Claims

1. A method for fabricating a thin film transistor in conjunction with a power MOSFET transistor, wherein the thin film transistor is a dual gate thin film transistor capable of driving the power MOSFET transistor, which comprises the steps of:

providing a semiconductor substrate of N+ conductivity type having an epitaxial layer of N conductivity type disposed thereon, the epitaxial layer having a top surface;

covering the top surface of the epitaxial layer with a first layer of dielectric material;

forming at least three openings in the first layer of dielectric material wherein a first opening exposes a first portion of the top surface of the epitaxial layer, a second opening exposes a second portion of the top surface of the epitaxial layer, and a third opening exposes a third portion of the top surface of the epitaxial layer;

forming a first doped region of P conductivity type in the epitaxial layer through the first opening and a second doped region of P conductivity type in the epitaxial layer through the second opening, wherein the first doped region and the second doped region extend to the surface;

forming a third doped region of N conductivity type in the epitaxial layer through the third opening, the third doped region extending to the surface;

providing a region of N conductivity type within the second doped region of P conductivity type, the region extending to the surface;

providing a dielectric material in a portion of at least the first opening wherein a section of the dielectric material in the portion of the at least the first opening serves as a protective film;

removing a portion of the first layer of dielectric material from the top surface of the epitaxial layer of a power MOSFET active area and a dual gate thin film transistor active area, wherein the first layer of dielectric material remains in a region surrounding the third opening;

forming a second layer of dielectric material on the top surface of the epitaxial layer wherein the second layer of dielectric material has a top surface;

providing a layer of polysilicon having at least one opening extending to the first doped region;

forming an island of polysilicon above a portion of the second doped region;

providing an impurity material of P conductivity type into the at least one opening;

providing a fourth doped region and a fifth doped region of N conductivity type within the first doped region of P conductivity type extending to the surface of the epitaxial layer;

providing an impurity material of a first conductivity type in a first portion and a second portion of the island of polysilicon wherein the island of polysilicon has a third portion which is sandwiched between and contiguous with the first portion and the second portion;

the protective film from the portion of the at least the first opening;

removing providing a third layer of dielectric material on the exposed portions of the second layer of dielectric material, the layer of polysilicon, the first island of polysilicon, and in the at least one opening;

providing a fourth layer of dielectric material wherein the fourth layer of dielectric material covers the top surface of the third portion and sections of the first and the second portions of the island of polysilicon;

providing a bias electrode, wherein the bias electrode contacts the third doped region;

providing a power MOSFET gate electrode wherein the power MOSFET gate electrode contacts the layer of polysilicon;

providing a power MOSFET source electrode wherein the source electrode contacts the epitaxial layer having the fourth and fifth doped regions and the top surface of the epitaxial layer therebetween;

providing a drain electrode on a backside surface of the semiconductor substrate of N conductivity type;

providing a first gate electrode for the thin film transistor wherein the first gate electrode contacts the second doped region;

providing a second gate electrode on the fourth layer of dielectric material which is above the third portion of the first island of polysilicon;

providing a source electrode to the thin film transistor; and

providing a drain electrode to the thin film transistor.

2. The method for fabricating the thin film transistor in conjunction with a power MOSFET transistor of claim 1 further including the step of providing a grounding electrode to the second doped region of P conductivity type.

3. The method for fabricating the thin film transistor in conjunction with a power MOSFET transistor of claim 1 further including the step of providing N+ conductivity type as the first conductivity type.

4. The method for fabricating the thin film transistor in conjunction with a power MOSFET transistor of claim 3 including the step of providing the third portion of the first island of polysilicon as N- conductivity type.

5. The method for fabricating the thin film transistor in conjunction with a power MOSFET transistor of claim 3 further including the step of providing the third portion of the first island of polysilicon as P- conductivity type.

6. The method for fabricating the thin film transistor in conjunction with a power MOSFET transistor of claim 1 further including the step of providing the P+ conductivity type as the first conductivity type.

7. The method for fabricating the thin film transistor in conjunction with a power MOSFET transistor of claim 6 further including the step of providing the third portion of the first island of polysilicon as P- conductivity type.

8. The method for fabricating the thin film transistor in conjunction with a power MOSFET transistor of claim 6 further including the step of providing the third portion of the first island of polysilicon as N- conductivity type.

9. A method for manufacturing a power MOSFET transistor having an integrated thin film transistor, which comprises the steps of:

providing a monocrystalline semiconductor material of a first conductivity type having a power MOSFET active area and a thin film transistor active area wherein the power MOSFET active area comprises a first region of a second conductivity type, the first region extending to a surface of the semiconductor material, the thin film transistor active area comprises a second region of the second conductivity type, the second region extending to

forming a region of the first conductivity type the surface of the semiconductor material;

within the thin film transistor active area extending to the surface of the semiconductor material;

providing a layer of dielectric material on the surface of the semiconductor material housing the power MOSFET active area and on the surface of the semiconductor material housing the thin film transistor active area;

providing a layer of polysilicon over the layer of dielectric material;

forming at least one opening in the layer of polysilicon over a portion of the first region of impurity material;

providing at least one region of impurity material of the second conductivity type through the at least one opening;

forming an island of polysilicon wherein the island is above the second region;

forming a thin film transistor from the island of polysilicon wherein the thin film transistor comprises a source electrode, a drain electrode, and a second gate electrode;

forming a first gate for the thin film transistor wherein the second region of the semiconductor material serves as the first gate;

providing a power MOSFET source electrode wherein the source electrode contacts the first region of impurity material through the at least one opening in the layer of polysilicon;

providing a power MOSFET gate electrode wherein the gate electrode contacts a portion of the layer of polysilicon; and

providing a power MOSFET drain electrode on a back side of the semiconductor material of first conductivity type.

10. The method for manufacturing the power MOSFET transistor having the integrated thin film transistor of claim 9 further including the step of providing N+ conductivity type as a conductivity type of the first and of the second portions of the island of polysilicon and further providing N- conductivity type as the conductivity type of the third portion of the island of polysilicon.

11. The method for manufacturing the power MOSFET transistor having the integrated thin film transistor of claim 10 further including the step of providing P- conductivity type as the conductivity type for the third portion of the island of polysilicon.

12. The method for manufacturing the power MOSFET transistor having the integrated thin film transistor of claim 9 further including the step of providing P+ conductivity as the conductivity type of the first and of the second portions of the island of polysilicon and further providing P- conductivity type as the conductivity type of the third portion of the island of polysilicon.

13. The method for manufacturing the power MOSFET transistor having the integrated thin film transistor of claim 12 further including the step of providing N- conductivity type as the conductivity type of the third portion of the island of polysilicon.

14. The method for manufacturing the power MOSFET transistor having the integrated thin film transistor of claim 9 further including the step of providing a second bias electrode wherein the second bias electrode contacts the second region of the second conductivity type of the dual gate thin film transistor active area.

15. The method for manufacturing the power MOSFET transistor having the integrated thin film transistor of claim 9 further including the step of providing a bias contact region in the semiconductor material of the first conductivity type comprising a third region of the first conductivity type extending to the surface of the semiconductor material.

16. A method of fabricating a power MOSFET transistor capable of high speed switching, which comprises:

providing a monocrystalline semiconductor substrate;

forming a power MOSFET transistor on a first portion of the monocrystalline semiconductor substrate wherein the monocrystalline semiconductor substrate houses a drain region and a source region, and a power MOSFET gate is separated from the source region and the drain region by a first gate dielectric;

forming a dual gate thin film transistor on a second portion of the monocrystalline semiconductor substrate wherein the second portion of the monocrystalline semiconductor substrate serves as a first gate of the dual gate thin film transistor, and an island of polysilicon houses the dual gate thin film transistor source region and the dual gate thin film transistor drain region; and

forming a dual gate thin film transistor second gate above the island of polysilicon wherein the second gate is separated from the island of polysilicon by a second gate dielectric.

17. The method of fabricating a power MOSFET transistor of claim 16 further including forming the dual gate thin film transistor second gate from metal.

18. The method of fabricating a power MOSFET transistor of claim 16 further including forming the power MOSFET gate and the dual gate thin film transistor second gate from polysilicon.