Integrated circuit bus structure

• US 5,266,833 A
• Filed: 03/30/1992
• Issued: 11/30/1993
• Est. Priority Date: 03/30/1992
• Status: Expired due to Fees

• Current Assignee: David F. Capps
• Original Assignee: David F. Capps
• Inventors: Capps, David F.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): BROWN, PETER T
• Application Number:
  US07/859,664
• Time in Patent Office: 610 Days
• Field of Search: 257/723, 257/725, 257/690, 257/691, 257/698, 257/666, 257/685, 257/686, 257/694, 257/695, 257/773
• US Class Current: 257/690
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4917 Crossed wires
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

An integrated bus structure forms a multi-bit, parallel electrical signal bus between a plurality of integrated circuit dies. In one embodiment, the integrated circuit dies are disposed in a spaced, parallel arrangement and have terminal pads mounted at peripheral edges thereof and disposed in a predetermined positional and functional relationship. Electrical conductors interconnect the same positionally arranged terminal pad on each of the plurality of integrated circuit dies to form a parallel, multi-bit, bus arrangement. In another embodiment, at least one integrated circuit is mounted on a support member. The mounting pads on each integrated circuit die are electrically connected to terminal pads formed on the peripheral edge of each support member. Electrical conductors interconnect the same positionally arranged terminal pad on each of a plurality of support members to interconnect the integrated circuit dies on each support member in a parallel bus arrangement.

Claims

1. A bus structure for an electronic system formed of a plurality of discrete integrated circuits performing different and at least certain of data processing, addressing, memory, and input/output signal conditioning functions, the bus structure comprising:

a plurality of semiconductor integrated circuit dies each having first and second opposed major surfaces and a peripheral edge formed therebetween, the plurality of integrated circuit dies disposed in a spaced, parallel arrangement;

integrated circuitry formed on each integrated circuit die for performing at lest one of data processing, addressing, memory and input/output signal conditioning functions, the integrated circuitry differing on at least certain of the integrated circuit dies;

each of the integrated circuit dies including a plurality of terminal pads disposed on the peripheral edge thereof and electrically connected to the integrated circuitry on each integrated circuit die;

the terminal pads on each integrated circuit die being arranged in a predetermined, positional electrical signal bus arrangement identical for all of the integrated circuit dies in the electronic system for electrical signal communication to and from each of the plurality of integrated circuit dies; and

electrical conductor means, disposed in electrical signal communication with at least certain of the terminal pads on certain of the integrated circuit dies, to form a multi-bit, parallel bus interconnecting each of the plurality of integrated circuit dies in the electronic system.

2. The bus structure of claim 1 further including:

electrical insulator members disposed between adjacent ones of the integrated circuit dies.

3. The bus structure of claim 1 wherein the electrical conductor means comprises:

a plurality of rigid, planar, electrical conductors, each spanning and contacting the same one positionally located terminal pad on each of the integrated circuit dies.

4. The bus structure of claim 3 further including:

electrical insulator members disposed between adjacent electrical conductors.

5. The bus structure of claim 1 wherein the electrical conductor means extends over a portion of the peripheral edge of each of the integrated circuit dies.

6. The bus structure of claim 1 wherein the electrical conductor means extends over substantially all of the peripheral edge of each of the integrated circuit dies.

7. The bus structure of claim 1 wherein:

the terminal pads are integrally formed with each integrated circuit die and extend across the peripheral edge of each integrated circuit die.

8. An integrated circuit bus structure comprising:

a plurality of semiconductor integrated circuit dies each having first and second opposed major surfaces and a peripheral edge formed therebetween, the plurality of integrated circuit dies disposed in a spaced, parallel arrangement;

each of the integrated circuit dies including a plurality of terminal pads disposed on the peripheral edge thereof and electrically connected to the circuitry on each integrated circuit die;

the terminal pads on each integrated circuit die being arranged in a predetermined, positional electrical signal bus arrangement identical for all of the integrated circuit dies for electrical signal communication to and from each of the plurality of integrated circuit dies, the terminal pads being exposed to a top and a bottom surface of each integrated circuit die; and

electrical conductor means, disposed in electrical signal communication with at least certain of the terminal pads on certain of the integrated circuit dies, to form a multi-bit, parallel bus interconnecting each of the plurality of integrated circuit dies.

9. An integrated circuit bus structure comprising:

a plurality of semiconductor integrated circuit dies each having first and second opposed major surfaces and a peripheral edge formed therebetween, the plurality of integrated circuit dies disposed in a spaced, parallel arrangement;

each of the integrated circuit dies including a plurality of terminal pads disposed on the peripheral edge thereof and electrically connected to the circuitry on each integrated circuit die;

the terminal pads including electrically conductive pads mounted on the peripheral edges of each integrated circuit die and extending from a top to a bottom surface of each integrated circuit die and over the peripheral edge of each integrated circuit die;

the terminal pads on each integrated circuit die being arranged in a predetermined, positional electrical signal bus arrangement identical for all of the integrated circuit dies for electrical signal communication to and from each of the plurality of integrated circuit dies; and

electrical conductor means, disposed in electrical signal communication with at least certain of the terminal pads on certain of the integrated circuit dies, to form a multi-bit, parallel bus interconnecting each of the plurality of integrated circuit dies.