Test wafer for diagnosing flaws in an integrated circuit fabrication process that cause A-C defects

• US 5,266,890 A
• Filed: 06/26/1992
• Issued: 11/30/1993
• Est. Priority Date: 06/26/1992
• Status: Expired due to Fees

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Kumbasar, Cevat, Shanks, Roy R., Wei, Steven S., Levi, Jonathan A., Petschauer, Richard J.
• Primary Examiner(s): NGUYEN, VINH P
• Application Number:
  US07/905,596
• Time in Patent Office: 522 Days
• Field of Search: 324/158 R, 324/158 T, 324/158 F, 324/73.1, 371/21.2, 371/22.3, 371/22.6, 437/8, 257/48, 368/113
• US Class Current: 324/762.05
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

An integrated circuit test wafer quickly detects A-C defects in any process by which the wafer is fabricated. This test wafer includes a semiconductor substrate having a major surface, and a diagnostic circuit that is repeatedly integrated over most of the wafer'"'"'s surface. Each diagnostic circuit includes: a) a plurality of ring oscillators which generate respective cyclic output signals; b) an addressing circuit that receives external input signals and in response selects an output signal from any particular ring oscillator of the plurality; c) a timing circuit that generates a timing signal with a certain time period; and, d) a counting circuit that counts the number of cycles that occur in the selected output signal during the time period and provides that number as an output. By comparing the relative or absolute speeds of all of the ring oscillators, a ring oscillator with an A-C defect is detected; and, a defective ring oscillator can then be analyzed under an E-beam microscope to determine the defects cause. Preferably, the ring oscillators occupy at least 90% of the test wafers surface so that A-C defects are detected even when they are sparsely distributed on the test wafer.

Claims

1. An integrated circuit test wafer, which detects flaws in any process by which the wafer is fabricated, comprising:

a semiconductor substrate having a major surface;

multiple copies of a diagnostic circuit that are integrated over most of said surface;

each copy of said diagnostic circuit including-

a plurality of ring oscillators which generate respective cyclic output signals;

an addressing circuit, coupled to said ring osciallators, that receives external input signals and in response selects an output signal from any particular ring oscillator of said plurality;

a timing circuit that generates a timing signal with a certain time period; and

,

a counting circuit, coupled to said timing circuit and said addressing circuit, that counts the number of cycles that occur in the selected output signal during said time period and provides that number as an output.

2. A test wafer according to claim 1 wherein said timing circuit includes a reference ring oscillator which generates a cyclic reference signal and a reference counter which generates said timing signal by counting a predetermined number of cycles in said reference signal.

3. A test wafer according to claim 2 wherein said reference counter counts at least one-hundred cycles of said reference signal to generate said timing signal.

4. A test wafer according to claim 1 wherein said timing circuit includes a logic gate which receives a cyclic reference signal from an external source, and a reference counter which generates said timing signal by counting a predetermined number of cycles in said reference signal.

5. A test wafer according to claim 4 wherein said reference counter counts at least one-hundred cycles of said reference signal to generate said timing signal.

6. A test wafer according to claim 1 wherein said diagnostic circuit is repeated on at least 90% of the major surface of said substrate.

7. A test wafer according to claim 1 wherein said plurality of ring oscillators are repeated on at least 90% of the major surface of said substrate.

8. A test wafer according to claim 1 wherein each ring oscillator of said plurality includes a serial chain of at least five logic modules that each perform a different logic function.

9. A test wafer according to claim 1 wherein each ring oscillator of said plurality includes a serial string of logic modules;

and, the number of modules in each string are not the same.

10. A test wafer according to claim 1 wherein each ring oscillator of said plurality includes a serial string of logic modules;

and, the serial interconnections between the modules of each string are not the same length.