Method for VLSI layout pattern compaction by using direct access memory

• US 5,267,177 A
• Filed: 04/17/1991
• Issued: 11/30/1993
• Est. Priority Date: 04/17/1990
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Toyonaga, Masahiko, Sato, Koichi, Akino, Toshiro
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US07/686,461
• Time in Patent Office: 958 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/122
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method for layout compaction which comprises steps of establishing storage areas in a direct access memory as a boundary information memory to which geometrical information on boundaries of a layout is written, searching layout elements of groups adjoining the boundaries of the layout and performing a processing of packing layout elements in a bottom boundary region of the layout and of packing layout elements in a top boundary region of the layout by using the boundary information memory. Thereby, a compaction of the layout can be performed at a high speed.

Claims

1. A computer implemented method for layout compaction for generating a minimum layout pattern of an integrated circuit which follows a predetermined design rule by reducing unnecessary spaces in a layout of the integrated circuit as much as possible, said method comprising using a programmed computer to implement the steps of:

establishing storage areas in a direct access memory as a boundary information memory to which geometrical information on bottom and top boundaries of the layout is written;

storing the geometrical information in the storage areas of the direct access memory;

performing a squeeze-down processing by reading the boundary information memory from the storage areas of the direct access memory and searching a layout area for layout elements next to the bottom boundary according to the boundary information and moving each layout element to a position next to the bottom boundary following the design rule and updating the boundary information; and

performing a lift-up processing by reading the boundary information from the storage areas of the direct access memory and searching a layout area for layout elements next to the top boundary and moving each layout element to a position following the design rule so as to reduce useless bends and updating the boundary information.

2. A computer implemented method for layout compaction for generating a minimum layout pattern of an integrated circuit which follows a predetermined design rule by reducing unnecessary spaces in a layout of the integrated circuit as much as possible, said method comprising using a programmed computer to implement steps of:

classifying layout elements in terms of coordinates in a direction of height into groups of layout elements of a same height;

establishing storage areas in a direct access memory as a boundary information memory for writing therein geometrical information on boundaries of a layout;

performing a squeeze-down processing to squeeze down each group of the layout elements which have a same height in a y-coordinate according to the design rule by scanning a layout area from a bottom boundary of the layout area to a top boundary by reading boundary information from the memory; and

performing a lift-up processing to lift up each group of the layout elements which is employed in the squeeze-down processing, so as to reduce useless bends by scanning the layout area from the top boundary of the layout area to the bottom boundary of the layout area by reading the boundary information from the memory.

3. The computer implemented method of claim 2, wherein the step of performing the squeeze-down processing comprises the further steps of moving an element of a group to a position adjacent to the bottom boundary in accordance with said design rule, and updating the geometrical information on the bottom boundary to include the element moved to the position adjacent to the bottom boundary.

4. A computer implemented method for layout compaction for generating a minimum layout pattern of an integrated circuit which follows a predetermined design rule by reducing unnecessary spaces in a layout of the integrated circuit as much as possible, said method comprising using a programmed computer to implement steps of:

classifying layout elements included in the layout of the integrated circuit in terms of coordinates in a direction of height into groups of layout elements of a same height;

establishing storage areas in a direct access memory as a boundary information memory to which geometrical information on boundaries of a layout is written;

storing the geometrical information in the storage areas of the direct access memory;

assigning programmed processors to the groups of the layout elements obtained by the classification, respectively; and

performing a squeeze-down processing and a lift-up processing on each group of the layout elements obtained by the classification independently from the processings on the other groups of layout elements by providing a delay among the processings effected by the processors on the groups of layout elements, each of the processors performing the squeeze-down processing and the lift-up processing by reading and updating the boundary information stored in the storage areas of the direct access memory.

5. A computer implemented method for layout compaction for generating a minimum layout pattern of an integrated circuit which follows a predetermined design rule by reducing unnecessary spaces in a layout of the integrated circuit as much as possible, said method comprising using a programmed computer to implement steps of:

classifying layout elements included in the layout of the integrated circuit in terms of coordinates in a direction of height into groups of layout elements of a same height;

establishing storage areas in a direct access memory as a boundary information memory to which geometrical information on bottom and top boundaries of a layout is written;

storing the geometrical information in the storage areas of the direct access memory;

performing the squeeze-down processing by reading boundary information from the storage areas of the direct access memory and searching a layout area for layout elements of each group, which have a same height in the direction of height and are next to the bottom boundary, according to the boundary information and moving each layout element of every group to a position next to the bottom boundary following the design rule and updating the boundary information; and

performing the lift-up processing by reading the boundary information from the storage areas of the direct access memory and searching a layout area for layout elements next to the top boundary and moving each layout element to a position following the design rule so as to reduce useless bends and updating the boundary information.

6. The computer implemented method of claim 5, wherein the step of performing the squeeze-down processing comprises the further step of establishing bending points in wiring elements.

7. The computer implemented method of claim 6, wherein the step of establishing bending points comprises moving a portion of a horizontal wiring element to the bottom boundary and establishing a vertical wiring element to connect the moved portion to a remaining portion of the wiring element.