High voltage boosted word line supply charge pump regulator for DRAM
First Claim
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1. A dynamic random access memory (DRAM) word line supply comprising:
- (a) a voltage supply Vpp increasing from a voltage level insufficient to enable a memory cell access transistor for the word line toward a voltage level sufficient to enable said access transistor, for connection to the word line from time to time,(b) the memory cell access transistor for connecting a memory cell capacitor to a bit line, having a gate connected to the word line,(c) a sample transistor similar to the memory cell access transistor;
(d) means for applying the increasing voltage supply to the sample transistor for causing the sample transistor to conduct, under voltage supply conditions similar to those required by the memory cell access transistor,(e) means for inhibiting increase of the voltage supply upon turn-on of the sample transistor,whereby the voltage supply having the voltage level sufficient to turn-on the memory cell access transistor is provided for connection to the word line.
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Abstract
A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by Vtn as in the prior art. The boosting capacitors are charged by Vdd, thus eliminating drift tracking problems associated with clock boosting sources and Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.
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6 Claims
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1. A dynamic random access memory (DRAM) word line supply comprising:
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(a) a voltage supply Vpp increasing from a voltage level insufficient to enable a memory cell access transistor for the word line toward a voltage level sufficient to enable said access transistor, for connection to the word line from time to time, (b) the memory cell access transistor for connecting a memory cell capacitor to a bit line, having a gate connected to the word line, (c) a sample transistor similar to the memory cell access transistor; (d) means for applying the increasing voltage supply to the sample transistor for causing the sample transistor to conduct, under voltage supply conditions similar to those required by the memory cell access transistor, (e) means for inhibiting increase of the voltage supply upon turn-on of the sample transistor, whereby the voltage supply having the voltage level sufficient to turn-on the memory cell access transistor is provided for connection to the word line. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification