SRAM with flash clear for selectable I/OS

• US 5,267,210 A
• Filed: 03/03/1993
• Issued: 11/30/1993
• Est. Priority Date: 05/18/1988
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: McClure, David C., Lysinger, Mark A.
• Primary Examiner(s): Kriess, Kevin A.
• Application Number:
  US08/025,894
• Time in Patent Office: 272 Days
• Field of Search: 395/400, 395/425, 395/750, 365/218, 365/195, 365/189.11, 365/182, 365/184, 365/185, 307/465
• US Class Current: 365/218
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

A static random access memory having multiple I/Os includes a memory array (10) of memory cells (42) with columns that are selectively clearable as a function of the associated I/O. The columns are arranged in pairs (34) with each column in the pair (34) associated with the same I/O. A clear signal is input thereto on a line (28) and driven by a driver (30). The clear signal is only associated with the pairs (34) associated with a selected I/O. The remaining columns of memory cells associated with unselected I/Os are not cleared.

Claims

1. A memory array with selectively clearable memory cells, comprising:

an array of memory cells arranged in rows and columns, each of said rows of memory cells associated with a separate row address and said columns arranged in predetermined groups of an equal number of said columns, wherein the columns of a selected group are further arranged in pairs with each pair sharing a common conductive run, and wherein each of the columns within said groups are associated with a separate column subaddress and arranged in a predetermined sequence within said groups with each of said groups associated with a predetermined column address sequence;

each of said memory cells operable to store first and second logic states therein and each having a flash clear input for forcing the logic state stored therein to said first logic state in response to receiving a flash clear signal, the flash clear inputs for said memory cells in a given one of said columns being commonly connected together by the common conductive run shared with the paired column;

row address decode means for receiving and decoding an external row address and accessing the associated one of said rows of memory cells;

column address decode means for receiving and decoding an external column address and selecting the associated one of said groups of columns of said memory cells;

select means for receiving the flash clear signal and routing it to the common conductive runs associated with predetermined groups of columns in said predetermined sequence such that all of said columns associated with said selected column address have the logic states in the associated ones of said memory cells forced to said first logic state when said flash clear signal is generated independent of the value of the bit lines; and

I/O means for interfacing with the accessed ones of said memory cells for inputting data thereto for a Write operation and outputting data therefrom for a Read operation;

wherein the flash clear signal has a voltage equal to either a logical one or a logical zero as stored in the array.

2. The memory of claim 1 wherein said memory cells are static memory cells.

3. The memory of claim 1 wherein said common conductive runs have a distributed capacitance associated therewith and said selection means comprises:

a second conductive run having a distributed capacitance associated therewith and disposed proximate to each of said common conductive runs;

interconnection means for selectively interconnecting the ones of said common conductive runs associated with said selected columns with said second conductive run; and

driver means for driving said second conductive run with said flash clear signal and interconnected ones of said common conductive runs.

4. The memory of claim 1 wherein:

said flash clear signal has a first state at a first voltage level and a second state at a second voltage level and each of said memory cells is operable to force the logic state stored therein to said first logic state when said first voltage level is applied to the flash clear thereof, and said memory cells not having the logic state thereof altered when said second voltage level is applied to the flash clear input thereof; and

said select means is operable to apply said first voltage level to the flash clear inputs of said memory cells in the selected ones of said columns and said second voltage level to the flash clear inputs of said memory cells in the unselected ones of said columns when said flash clear signal is present.

5. The memory of claim 4 wherein said select means comprises:

a second conductive run disposed adjacent to said array proximate to each of said common conductive runs;

means for applying said first voltage level to said second conductive run when said flash clear signal is present;

first means for connecting said second conductive run to the common conductive runs.

6. The memory of claim 5 wherein said means for applying said first voltage level to said second conductive run comprises a driver having the input thereof interfaced with said flash clear input and the output thereof operable to drive said second conductive run wherein said common and second conductive runs have a distributed capacitance associated therewith.

7. The memory of claim 5 wherein said second conductive run is disposed adjacent to said array and perpendicular to said common conductive runs, and said first means for connecting comprises a conductive interconnect between the ones of said common conductive runs said second conductive run.

8. The memory of claim 4 wherein each of said memory cells comprises:

a first sense node;

a second sense node;

a first transistor having a source-to-drain path connected between said first sense node and a node providing a second voltage level and the gate thereof connected to said second sense node;

a second transistor having a source-to-drain path thereof connected between said second sense node and the flash clear input and the gate thereof connected to said first sense node;

first pull up means connected between said first sense node and a power supply for pulling said first sense node to the voltage of said power supply when said first transistor is not conducting;

second pull up means connected between said second sense node and said positive supply for pulling said second sense node to the voltage of said power supply when said first transistor is not conducting; and

an access transistor having the source-to-drain path thereof connected between said first sense node and said column address decode means and the gate thereof connected to said row address decode means;

wherein said first sense node is forced to a voltage level corresponding to said first logic state when the flash clear input is raised to said first voltage level.

9. The memory of claim 3, wherein the driver means comprises:

a plurality of driver circuits distributed along the second conductive run, wherein the driver circuits simultaneously drive a flash clear signal onto the second conductive run.

10. The memory array of claim 9, wherein the driver circuits are spaced at regular intervals along the second conductive run across one dimension of the array, and are aligned with all of the columns in the array, including those not connected to common conductive runs.

11. The memory of claim 5, wherein the driver comprises:

a plurality of driver circuits distributed along the second conductive run, wherein the driver circuits simultaneously drive a flash clear signal onto the second conductive run.

12. The memory array of claim 11, wherein the driver circuits are spaced at regular intervals along the second conductive run across one dimension of the array, and are aligned with all of the columns in the array, including those not connected to common conductive runs.

13. The memory array of claim 1, wherein each group of columns corresponds to a single data bit position, wherein the memory cells in at least one selected group of columns is forced to the first logic state when the flash clear signal is generated, and wherein the memory cells in the remaining groups of columns do not change value when the flash clear signal is generated.

14. The memory array of claim 13, wherein the at least one group of selected columns comprises exactly one group of columns.

15. A memory array with selectively clearable memory cells, comprising:

an array of SRAM cells arranged in rows and columns, wherein the columns are divided into groups representing a plurality of bit positions;

means for selecting columns within each group utilizing a subcolumn address;

each of the memory cells operable to store first and second logic states therein, and those cells in the columns of at least one group having flash clear inputs for forcing the logic state within such cells to the first logic state in response to receiving a flash clear signal at the flash clear input;

a common conductive run between pairs of the columns having cells with flash clear inputs, wherein the flash clear inputs for the cells in the pair are connected to the common conductive run between them; and

select means for receiving a flash clear signal, and driving the common conductive runs with a flash clear signal so as to force the cells in the pairs of columns associated therewith to the first logic state.

16. The memory array of claim 15, further comprising:

a second conductive run disposed orthogonally to the common conductive runs in proximity therewith;

interconnection means for selectively interconnecting the common conductive runs with the second conductive run; and

driver means for driving the second conductive run with the flash clear signal.

17. The memory array of claim 16, wherein the driver means comprises:

a plurality of driver circuits distributed along the second conductive run, wherein the driver circuits simultaneously drive a flash clear signal onto the second conductive run.

18. The memory array of claim 17, wherein the driver circuits are spaced at regular intervals along the second conductive run across one dimension of the array, and are aligned with all of the columns in the array, including those not connected to common conductive runs.

19. The memory array of claim 15, wherein each group of columns corresponds to a single data bit position, wherein the memory cells in at least one selected group of columns is forced to the first logic state when the flash clear signal is generated, and wherein the memory cells in the remaining groups of columns do not change value when the flash clear signal is generated.

20. The memory array of claim 19, wherein the at least one group of selected columns comprises exactly one group of columns.