Highly compact EPROM and flash EEPROM devices

• US 5,268,318 A
• Filed: 10/15/1991
• Issued: 12/07/1993
• Est. Priority Date: 06/08/1988
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Eliyahou Harari
• Inventors: Harari, Eliyahou
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US07/776,826
• Time in Patent Office: 784 Days
• Field of Search: 437/43, 437/48, 437/52, 357/23.5, 365/185, 257/298, 257/320
• US Class Current: 438/263
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5613 Multilevel memory cell with additional gates, not being floating or control gates
• CPC Class Codes: G11C 2211/5631 Concurrent multilevel reading of more than one cell
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 438/972 : Stored charge erasure

Abstract

Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Claims

1. A method of forming an array of split-channel flash electrically programmable read only memory cells on a semiconductor substrate surface, comprising the steps of:

providing a plurality of parallel elongated source and drain regions spaced across the substrate surface, a length of said regions extending in a first direction and being spaced apart in a second direction to form channel regions therebetween, said first and second directions being substantially orthogonal to each other,

forming a first plurality of continuous parallel conductive strips with their lengths extending in said first direction and having widths extending in said second direction part way across said channels, thereby to leave a portion of the channel regions uncovered of said first strips, said first strips being insulated from said substrate surface by a thin gate dielectric layer,

forming a second plurality of continuous parallel conductive strips with their lengths extending in said second direction and being spaced apart in said first direction, said second strips being insulated from said first strips and from the exposed substrate surface therebetween,

removing at least a portion of said first strips inbetween said second strips by using said second strips as a mask in a manner that the remaining portions of the first strips have edges in said first direction which are aligned with edges of said second strips under which they lie, thereby to form isolated floating gates from said first strips that underlay said second strips as control gates, and

forming a third plurality of continuous parallel conductive strips with their lengths extending in said second direction and positioned in said first direction inbetween said second strips, said third strips forming erase gates that are positioned adjacent edges of floating gates with a tunnel dielectric therebetween.

2. The method according to claim 1 wherein the step of removing at least a portion of the first strips includes ethching said first strips with only said second strips forming said mask.

3. The method according to claim 1 wherein the step of removing at least a portion of the first strips includes etching said first strips with said second strips and a dielectric spacer along edges of said second strips forming said mask.

4. The method according to claim 1 wherein the steps of forming the first, second and third plurality of conductive strips include forming respective first, second and third different layers of polysilicon material.

5. A method of forming an array of split-channel flash electrically programmable read only memory cells on a semiconductor substrate surface comprising the steps of:

forming a plurality of parallel elongated source and drain regions beneath the substrate surface and spaced thereacross, a length of said regions extending in a first direction and being spaced apart in a second direction to form channel regions therebetween, said first and second directions being substantially orthogonal to each other,

forming a first dielectric layer on said semiconductor surface,

forming on said first dielectric layer a first plurality of continuous parallel conductive strips with their lengths extending in said first direction and having widths extending in said second direction part way across said channels, thereby to leave a portion of the channel regions uncovered of said first strips,

forming a second dielectric layer on said first plurality of conductive strips,

forming on said first and second dielectric layers a second plurality of continuous parallel conductive strips with their lengths extending in said second direction and being spaced apart in said first direction, whereby said second strips are insulated from said first strips and from regions of the substrate surface therebetween,

removing at least a portion of said first strips in between said second strips by using said second strips as a mask in a manner to convert the first strips into isolated floating gates underlaying said second strips as control gates and having exposed surfaces in spaces between the control gates,

forming a third dielectric layer over at least said floating gate exposed ends, and

forming in spaces between said control gate a third plurality of continuous parallel conductive strips with their lengths extending in said second direction and in contact with said third dielectric layer that is carried by the floating gate exposed surfaces in such spaces.

6. The method according to claim 5 wherein the step of removing at least a portion of the first strips includes etching said first strips with only said second strips forming said mask.

7. The method according to claim 5 wherein the step of removing at least a portion of the first strips includes etching said first strips with said second strips and a dielectric spacer along edges of said second strips forming said mask.

8. The method according to claim 5 wherein the steps of forming the first, second and third plurality of conductive strips include forming respective first, second and third different layers of polysilicon material.