Method of fabricating an integrated circuit interconnection
First Claim
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1. A method of semiconductor integrated circuit fabrication comprising:
- forming a dielectric covering a raised first aluminum-rich conductor;
forming an opening in said dielectric, said opening exposing a portion of said first conductor;
forming a layer of refractory metal silicide upon said dielectric and within said opening and contacting said raised first conductor;
forming a layer of titanium nitride upon said layer of refractory metal silicide by reactive sputter deposition from a refractory metal target in a nitrogen atmosphere;
forming a second aluminum-rich conductive material layer contacting said titanium nitride layer within said opening and contacting said titanium nitride layer upon said dielectric;
patterning said second conductive layer and said titanium nitride layer and said refractory metal silicide layer to form a runner.
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Abstract
A conductive layer is formed beneath a runner in an integrated circuit. The conductive layer is also formed within vias. The conductive layer preserves electrical connection should the runner separate due, perhaps, to electromigration or stress voiding. The conductive layer also provides protection against various failures or defects which may occur in the runner material within the vias.
30 Citations
2 Claims
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1. A method of semiconductor integrated circuit fabrication comprising:
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forming a dielectric covering a raised first aluminum-rich conductor; forming an opening in said dielectric, said opening exposing a portion of said first conductor; forming a layer of refractory metal silicide upon said dielectric and within said opening and contacting said raised first conductor; forming a layer of titanium nitride upon said layer of refractory metal silicide by reactive sputter deposition from a refractory metal target in a nitrogen atmosphere; forming a second aluminum-rich conductive material layer contacting said titanium nitride layer within said opening and contacting said titanium nitride layer upon said dielectric; patterning said second conductive layer and said titanium nitride layer and said refractory metal silicide layer to form a runner.
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2. A method of semiconductor integrated circuit fabrication comprising:
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forming a dielectric layer covering a raised first aluminum-rich conductor; forming an opening in said dielectric layer, said opening exposing a portion of said first conductor; forming a layer of titanium nitride upon said dielectric and within said opening and contacting said first conductor; forming a refractory metal silicide material layer upon said layer of titanium nitride, said silicide being formed by inert sputter deposition from a refractory silicide target; forming a second aluminum-rich conductive material layer contacting said refractory metal silicide layer within said opening and contacting said refractory metal silicide layer upon said dielectric; patterning said second conductive material layer and said refractory metal silicide layer and said titanium nitride layer to form a runner.
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Specification