Device and method for automatically adjusting a phase-locked loop
First Claim
1. An automatic phase-locked loop (PLL) parameter adjusting device having a PLL error signal input, comprising:
- (A) integrating means (I), having an I input and an I output, the I input being operably coupled to receive the PLL error signal, for successively integrating the PLL error over a predetermined N sample interval and providing a sum signal at the I output, where N is a first preselected integer, and further being operably coupled to receive an output signal from an automatic decision means, for adjusting N in correspondence with said output signal,(B) a counting means (C), having a C input and a C output, being operably coupled to receive the I output signal, for counting K sum signals (where K is a second preselected integer) and recording and counting the sign of said signals to provide a counter comparator signal at the C output,(C) a threshold means (TH), having a TH input and a TH output, the TH input being operably coupled to receive the C output (counter comparator) signal, for comparing the C output (counter comparator) signal with a predetermined threshold value to provide a parameter modifications signal at the TH output, and(D) the automatic decision means (AD), having an AD input and at least first and second AD outputs, being operably coupled to receive the TH output signal, for;
(D1) adjusting N in accordance with a predetermined strategy and providing a first AD output signal representing the adjustment of N to the integrating means, and(D2) adjusting PLL parameter(s) in accordance with the predetermined strategy and providing AD output signal(s) that represent(s) the adjusted PLL parameter(s), being at least a second AD output signal, to the PLL.
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Accused Products
Abstract
A self-adjusting phase-locked loop (PLL) parameter adjusting device (APAD) (100) and method that automatically adjusts a phase-locked loop to provide tracking ability when and where needed, as opposed to utilizing a PLL adjusting device with preset parameters, thus maintaining minimal possible noise bandwidth. The method utilizes (1) successively integrating the PLL error output signal over a number of samples to provide a plurality of sums, (2) checking a predetermined number of sums and recording and counting the sign of each sum, (3) comparing the counted record to a predetermined threshold value, and (4) automatically adjusting PLL parameter(s) and the sample number in accordance with a predetermined strategy, such that adjusted PLL parameters are provided to the PLL.
14 Citations
20 Claims
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1. An automatic phase-locked loop (PLL) parameter adjusting device having a PLL error signal input, comprising:
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(A) integrating means (I), having an I input and an I output, the I input being operably coupled to receive the PLL error signal, for successively integrating the PLL error over a predetermined N sample interval and providing a sum signal at the I output, where N is a first preselected integer, and further being operably coupled to receive an output signal from an automatic decision means, for adjusting N in correspondence with said output signal, (B) a counting means (C), having a C input and a C output, being operably coupled to receive the I output signal, for counting K sum signals (where K is a second preselected integer) and recording and counting the sign of said signals to provide a counter comparator signal at the C output, (C) a threshold means (TH), having a TH input and a TH output, the TH input being operably coupled to receive the C output (counter comparator) signal, for comparing the C output (counter comparator) signal with a predetermined threshold value to provide a parameter modifications signal at the TH output, and (D) the automatic decision means (AD), having an AD input and at least first and second AD outputs, being operably coupled to receive the TH output signal, for; (D1) adjusting N in accordance with a predetermined strategy and providing a first AD output signal representing the adjustment of N to the integrating means, and (D2) adjusting PLL parameter(s) in accordance with the predetermined strategy and providing AD output signal(s) that represent(s) the adjusted PLL parameter(s), being at least a second AD output signal, to the PLL. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A system for regulating a voltage-controlled oscillator with an automatically adjusted phase-locked loop (PLL), the PLL having an input signal, comprising:
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(A) a PLL, having at least first and second PLL inputs and at least first and second PLL outputs, operably coupled to receive the input signal at the first PLL input, for providing a PLL error signal to an automatic PLL parameter adjusting unit as a first PLL output signal, receiving and utilizing adjusted PLL parameter(s) to provide an adjusted PLL signal to a voltage-controlled oscillator (VCO) means at the second PLL output. (B) the automatic PLL parameter adjusting unit (APA), having predetermined PLL parameters and having a first APA input and at least a first APA output, operably coupled to receive the PLL error signal at the first APA input, for automatically adjusting the predetermined PLL parameters in accordance with a predetermined strategy and providing signal(s) representing the adjusted PLL parameter(s) at APA output(s) that are operably coupled to PLL input(s), and (C) the voltage-controlled oscillator (VCO) means, having at least a first VCO input and a first VCO output, operably coupled to receive the adjusted PLL signal at the first VCO input, for tuning the VCO in accordance with a predetermined scheme to provide the first VCO output signal, wherein the automatic phase-locked loop (PLL) parameter adjusting unit that utilizes a PLL error signal, comprises; (A) integrating means (I), having an I input and an I output, the I input being operably coupled to receive the PLL error signal, for successively integrating the PLL error for a predetermined N sample interval and providing a sum signal at the I output, where N is a first preselected integer, (B) a counting means (C), having a C input and a C output, being operably coupled to receive the I output signal, for counting K sum signals (where K is a second preselected integer) and recording and counting the sign of said signals to provide a counter comparator signal at the C output, (C) a threshold means (TH), having a TH input and a TH output, the TH input being operably coupled to receive the C output (counter comparator) signal, for comparing the C output (counter comparator) signal with a predetermined threshold value to provide a parameter modification signal at the TH output, and (D) an automatic decision means (AD), having a AD input and at least first and second AD outputs, being operably coupled to receive the TH output signal, for; (D1) adjusting N in accordance with a predetermined strategy and providing a first AD output signal representing the adjustment of N to the integrating means, and (D2) adjusting PLL parameter(s) in accordance with the predetermined strategy and providing AD output signal(s) that represent(s) the adjusted PLL parameter(s), being at least a second AD output signal, to the PLL. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method for automatically adjusting parameters of a phase-locked loop (PLL) that has a PLL error output signal, comprising the steps of:
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(A) successively integrating the PLL error output signal over N samples to provide a sum, where N, is a first preselected integer, to provide a plurality of sums, (B) checking K sums, where K is a second preselected integer, and recording and counting the sign of each sum, (C) comparing the counted record to a predetermined threshold value, and (D) automatically adjusting PLL parameter(s) and N in accordance with a predetermined strategy based on the comparison, such that adjusted PLL parameters are provided to the PLL. - View Dependent Claims (17, 18, 19, 20)
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Specification