Flash EEPROM system and intelligent programming and erasing methods therefor

• US 5,268,870 A
• Filed: 08/06/1990
• Issued: 12/07/1993
• Est. Priority Date: 06/08/1988
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Eliyahou Harari
• Inventors: Harari, Eliyahou
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US07/563,287
• Time in Patent Office: 1,219 Days
• Field of Search: 365/218, 365/185, 365/184, 365/189.07, 365/236, 365/200, 371/10.1, 371/10.2, 371/10.3, 371/21.1, 371/21.2, 371/21.3, 371/21.4
• US Class Current: 365/185.09
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5613 Multilevel memory cell with additional gates, not being floating or control gates
• CPC Class Codes: G11C 2211/5631 Concurrent multilevel reading of more than one cell
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Individual records of the number of erase cycles experienced by blocks of flash EEPROM cells are kept, preferably as part of the blocks themselves, in order to maintain an endurance history of the cells within the blocks. A series of pulses of increasing voltage is applied during programming and erasing of the array. During erasing, specified cells within a block of cells being erased are read in-between the pulses, and the process is stopped when the specified cells are read to have reached a desired state or a maximum number of pulses is reached. The entire block is then read to determine the number of cells that have not been completely erased. The unerased cells are replaced by redundant cells unless there are too many unerased cells, in which case a flag is generated to indicate that the array may have reached its endurance limit. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Claims

1. A method of erasing to a target erased charge level an addressed block of cells in an array of columns and rows of electrically erasable ad programmable read only memory cells, each cell having a field effect transistor with a threshold voltage that is alterable by controlling a level of charge on a floating gate thereof, said method comprising the steps of:

applying to the cells of the addressed block of cells a controlled voltage for a time sufficient to alter their respective charge levels toward said target erased charge level,

thereafter reading the charge levels on the floating gates of a plurality of cells in the addressed block of cells that is substantially less than all of the cells in the addressed block of cells,

determining whether any one of a plurality of conditions has occurred with respect to said plurality of cells,

repeating as necessary the foregoing steps until it is determined that one of the plurality of conditions has occurred with respect to said plurality of cells,

thereafter reading the charge levels on the floating gates of the cells of the addressed block of cells,

thereafter determining the number of cells N in the addressed block of cells which have not reached said target erased charge level, and

thereafter comparing said number of cells N with an acceptable number X of unerased cells.

2. The method according to claim 1 which additionally comprises, after it is determined that one of the plurality of conditions has occurred with respect to said plurality of cells, a step of applying a further erase pulse to the addressed block of cells.

3. The method according to claim 1 which additionally comprises, in response to a determination in the comparing step that the number of cells N which have not reached the erased level exceeds the acceptable number X, an additional step of either (a) generating the address locations of the cells which have not reached the erased level if the number of cells N which have not reached the erased level is less than or equal to a second umber of cells that is higher than said acceptable number X, or (b) generating an endurance limit flag if the number of cells N which have not reached the erased level exceeds said second number of cells.

4. The method according to claim 1 wherein the plurality of conditions includes a condition of the number of cells N of the addressed block of cells which have not reached the target erased voltage level being less than or equal to an acceptable number of cells.

5. The method according to claim 1 wherein the step of reading the plurality of cells substantially less than all the cells of the addressed block includes reading at least one cell from each row and at least one cell from each column.

6. The method according to claim 5 wherein the step of reading the plurality of cells substantially less than all the cells of the addressed block further includes reading cells from a diagonal pattern across said array of cells.

7. A method of erasing a memory state from an addressed block of cells of an array of electrically erasable and programmable read only memory cells having means for addressing cells to program, read and erase their states, each cell having a field effect transistor with a natural threshold voltage that is alterable by controlling a level of charge on a floating gate thereof to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, said method comprising the steps of:

pulsing the addressed cells for a predetermined time and predetermined voltage sufficient to alter their respective threshold voltages toward an erased level but insufficient to completely reach an erased threshold level,

thereafter reading currents through a selected number of the addressed cells that is substantially less than the total number of addressed cells in order to ascertain their effective threshold voltages,

repeating the pulsing and reading steps a plurality of times until after any one of a plurality of conditions is first detected to have occurred, each repeat of the pulsing step increasing the predetermined voltage an increment above that of the previous pulsing step, and

after one of the plurality of conditions is first detected to have occurred, the method further comprising the steps of;

reading currents through the addressed cells, determining a number of cells N whose threshold levels have not reached the erased level, and

thereafter comparing the number of cells N which have not reached the erased level with an acceptable number X of unerased cells.

8. The method according to claim 7 which additionally comprises, in response to a determination in the comparing step that the number of cells N which have not reached the erased level exceeds the acceptable number X, an additional step of either (a) generating the address locations of the cells which have not reached the erased level if the number of cells N which have not reached the erased level is equal to or less than a second number of cells that is higher than said acceptable number X of cells, or (b) generating an endurance limit flag if the number of cells N which have not reached the erased level exceeds said second number of cells.

9. The method according to claim 8 wherein the reading step further includes reading cells from a diagonal pattern across said array of cells.

10. A method of erasing a memory state from an addressed block of cells of an array of electrically erasable and programmable read only memory cells having means for addressing cells to program, read and erase their states, each cell having a field effect transistor with a natural threshold voltage that is alterable by controlling a level of charge on a floating gate thereof to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, said method comprising the steps of:

pulsing the addressed cells for a predetermined time and predetermined voltage sufficient to alter their respective threshold voltages toward an erased level but insufficient to completely reach an erased threshold level,

thereafter reading currents through a selected number of cells in order to ascertain their effective threshold voltages,

repeating the pulsing and reading steps a plurality of times, each repeat of the pulsing step increasing the predetermined voltage an increment above that of the previous pulsing step, and terminating the pulsing and reading steps after an occurrence of any one of the following conditions;

the effective threshold voltage of each of said selected number of the addressed block of cells has reached the erased threshold level;

or

the pulsing step has bene repeated a preset maximum number of times;

or

a predetermined maximum voltage for a pulse has been reached in a most recent pulsing step;

or

a number of cells N of said selected number of cells which remain not fully erased is equal to or less than an acceptable number of unerased cells.

11. The method according to claim 10 wherein the increment of voltage during each successive repeated pulsing step is within a range of approximately 0.25 volt to one volt.

12. The method according to claim 10 which additionally comprises a step of applying a further erase pulse to the addressed cells after one of the plurality of conditions is first detected to have occurred.

13. The method according to claim 10 wherein each pulsing step includes a step of directing to the addressed cells a sequence of pulses, each respective pulse having a voltage level that is substantially equal to a voltage of a first pulse plus a fixed voltage increment times the number of the respective pulse in the sequence after the first pulse.

14. The method according to claim 10 further comprising an additional step of accumulating a count equal to a total number of erase cycles that have been experienced by the addressed block of cells.

15. The method according to claim 14 further comprising an additional step of storing said count in cells within said addressed block of cells, whereby said addressed block of cells has its erase cycle count provided separately from any other block of cells that are provided as part of the array.

16. The method according to claim 10 wherein the selected number of cells is significantly less than the total number of addressed cells.

17. The method according to claim 16 wherein the array of memory cells is arranged in a pattern of rows and columns, and wherein the reading step includes reading at least ne cell from each row and one cell from each column.

18. A method of erasing a memory state from an addressed block of cells of an array of electrically erasable and programmable read only memory cells having means for addressing cells to program, read and erase their state, each cell having a field effect transistor with a natural threshold voltage that is alterable by controlling a level of charge on a floating gate thereof to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, said method comprising the steps of:

pulsing the addressed cells for a predetermined time and predetermined voltage sufficient to alter their respective threshold voltages toward an erased level but insufficient to completely reach an erased threshold level,

thereafter reading currents through a selected number of cells that is substantially less than the total number of addressed cells in order to ascertain their effective threshold voltages,

repeating the pulsing and reading steps a plurality of times until after any one of a plurality of conditions is first detected to have occurred, each repeat of the pulsing step increasing the predetermined voltage an increment above that of the previous pulsing step, and

after one of the plurality of conditions is first detected to have occurred, determining a number N of cells whose threshold levels have not reached the erased level,

thereafter comparing the number N of cells which have not reached the erased level with an acceptable number X of unerased cells, and

in response to a determination in the comparing step that the number of cells N which ave not reached the erased level exceeds the acceptable number X, an additional step of either (a) generating the address locations of the dells which have not reached the erased level if the number of cells N which have not reached the erased level is equal to or less than a second number of cells that is higher than said acceptable number X of cells, or (b) generating an indication that the addressed cells have reached an endurance limit if the number of cells N which have not reached the level exceeds said second number of cells, wherein an erase cycle is completed.

19. The method according to claim 18, further comprising an additional step of accumulating a count equal to a total number of times that the addressed block of cells has been subjected to an erase cycle.

20. The method according to claim 19, further comprising an additional step of comparing said count with a set number to determine whether the addressed block of cells has reached an endurance limit.

21. A method of erasing to a target erased charge level an addressed block of a plurality of electrically erasable and programmable read only memory cells, each cell having a field effect transistor with a threshold voltage that is alterable by controlling a level of charge on a floating gate thereof, said method comprising the steps of:

applying to the cells of the addressed block of cells a controlled voltage for a time sufficient to alter their respective charge levels toward said target erased charge level,

thereafter reading the charge levels on the floating gates of a selected number of the addressed block of cells,

monitoring a number of cells N of said selected number of cells whose charge levels have not yet reached said target erased charge level, and

repeating the applying, reading and monitoring steps until it is determined during the monitoring step that either (1) the number of cells N of said selected number of cells whose charge levels have not reached said target erased charge level is equal to or less than an acceptable number X of cells, in which case the repeating of the applying, reading and monitoring steps is terminated, or (2) the repeating of the applying, reading nd monitoring steps has occurred more than a maximum number of times before the number of cells which have not reached the target erased charge level falls below said acceptable number X, in which case the repeating of the applying, reading and monitoring steps is terminated and the method continues by additionally including a step of either (a) generating the address locations of the cells which have not reached the target erased charge level if the number of cells N which have not reached the target erased charge level is equal to or less than a second number of cells that is higher than said acceptable number X of cells, or (b) generating an indication that the addressed block of cells has reached an endurance limit if the number of cells N which have not reached the target erased charge level exceeds said second number of cells such that the number of cells N which have not reached the target erased charge level is significantly larger than the acceptable number X of cells.

22. The method according to claim 21, further comprising an additional step of incrementing a running count by one in response to each termination of the erase cycle, whereby said running count provides an indication of the total number of erase cycles which the addressed block of cells has experienced.

23. The method according to claim 22, further comprising an additional step of comparing said running count with a set number to determine whether the addressed block of cells has reached an endurance limit.

24. A method of erasing an array of a plurality of electrically erasable and programmable read only memory (EEPROM) cells, each cell having a field effect transistor with a threshold voltage that is alterable by controlling a level of charge on a floating gate thereof and having an erase gate, said method comprising the steps of:

causing cells within distinct blocks of cells to be simultaneously erasable by subjecting the erase gates thereof to an erase voltage,

designating a plurality of cells in each block of cells for storing a number of erase cycles which that block has experienced,

reading, from the designated cells of a selected block to be erased, an experience number indicative of the number of erase cycles which the selected block has experienced

storing said experience number in a register,

thereafter subjecting said selected block to an erase cycle, thereby erasing said selected block,

thereafter incrementing said experience number by one, and

thereafter writing the incremented experience number from said register into said designated cells of said selected block.

25. The method according to claim 24 wherein the step of simultaneously subjecting the cells in said selected block to an erase voltage includes the steps of:

pulsing the erase gates of substantially all the cells in said selected bock for a predetermined time and voltage sufficient to alter the threshold voltages of their respective transistors but insufficient to completely erase the cells being pulsed,

thereafter determining the altered threshold voltages of the cells subjected to the pulsing step, and

repeating the pulsing and reading steps a plurality of times, each repeating of the pulsing step including pulsing substantially all the cells in said selected block with a voltage that is increased an increment above that of the previous pulsing step.