Digital beamforming and filtering circuit

• US 5,268,877 A
• Filed: 05/11/1992
• Issued: 12/07/1993
• Est. Priority Date: 05/11/1992
• Status: Expired due to Fees

• Current Assignee: NAVY, THE UNITED STATES OF AMERICA AS REPRSENTED BY THE SECRETARY OF THE
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Odell, Douglas L.
• Primary Examiner(s): Pihulic, Daniel T.
• Application Number:
  US07/880,824
• Time in Patent Office: 575 Days
• Field of Search: 367/103, 367/105, 367/7, 367/11, 73/626, 128/661.01, 342/417, 342/378, 342/157, 342/195, 364/724.01, 364/724.1, 364/413.13
• US Class Current: 367/103
• CPC Class Codes: G01S 3/8083 determining direction of source
• CPC Class Codes: G10K 11/346 using phase variation

Abstract

A beamformer system is disclosed which includes an array of sensors such asydrophones which produce signals from which information relating to a target is to be determined. The beamformer system includes a channel for each sensor, the channel including a varable length shift register which provides bulk delay to received signals, a FIR interpolation filter which provides vernier delay and shading. The system also includes a summation tree which adds the received signals and a sign extension/bit reversal filter to avoid authmetic overflow.

Claims

1. A circuit for enhancing the amplitude of a signal received by the circuit relative to ambient noise and directional interference comprising;

first means for providing a predetermined bulk delay to the signal received by the circuit,

second means including a sign extension/bit reversal filter for filtering signal data words received from the first means and,

third means for providing a predetermined vernier delay to the signal received from the second means, whereby a signal indicating the amplitude of the signal received by the is generated.

2. A circuit as set forth in claim 1 wherein the first means includes a variable length shift register.

3. A circuit as set forth in claim 1 and further including a summation tree which acts to sum the received signals.

4. A circuit as set forth in claim 1 wherein the third means includes a FIR interpolation filter.

5. A circuit for enhancing the amplitude of a signal received by the circuit relative to ambient noise and directional interference comprising;

first means for providing a predetermined bulk delay to the signal received by the circuit, second means for filtering signal data words received from the first means and, third means including a FIR interpolation filter for providing a predetermined vernier delay to the signal received from the second means, whereby a signal indicating the amplitude of the signal received by the circuit is generated.

6. A circuit as set forth in claim 5 wherein the second means includes a sign extension/bit reversal filter.

7. A circuit as set forth in claim 5 wherein the first means includes a variable length shift register.

8. A circuit as set forth in claim 5 and further including a summation tree which acts to sum the received signals.