Three dimensional multichip package methods of fabrication

• US 5,270,261 A
• Filed: 10/23/1992
• Issued: 12/14/1993
• Est. Priority Date: 09/13/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bertin, Claude L., White, Francis R., Kalter, Howard L., Kelley, Gordon A. Jr., van der Hoeven, Willem B., Farrar, Paul A. Sr.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Picardat, Kevin M.
• Application Number:
  US07/965,728
• Time in Patent Office: 417 Days
• Field of Search: 437/208, 437/209, 437/228, 437/974, 148/DIG. 135
• US Class Current: 438/109
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/135 Removal of substrate

Abstract

A fabrication method and resultant three-dimensional multichip package having a densely stacked array of semiconductor chips interconnected at least partially by means of a plurality of metallized trenches are disclosed. The fabrication method includes providing an integrated circuit chip having high aspect ratio metallized trenches therein extending from a first surface to a second surface thereof. An etch stop layer is provided proximate the termination position of the metallized trenches with the semiconductor substrate. Next the integrated circuit device is affixed to a carrier such that the surface of the supporting substrate is exposed and substrate is thinned from the integrated circuit device until exposing at least some of the plurality of metallized trenches therein. Electrical contact can thus be made to the active layer of the integrated circuit chip via the exposed metallized trenches. Specific details of the fabrication method and the resultant multichip package are set forth.

Claims

1. A method for packaging an integrated circuit device, said method comprising the steps of:

(a) providing an integrated circuit device having a first, upper surface and a second, lower surface, said device having an active layer adjacent said first surface and a substrate adjacent said second surface, said integrated circuit device further including a plurality of metallized trenches therein extending from said first surface through said active layer and only partially into said substrate, at least some of said plurality of metallized trenches being in electrical contact with the active layer of said integrated circuit device;

(b) affixing said integrated circuit device to a carrier such that said second surface is exposed and such that said active layer is protected; and

(c) thinning said substrate of the integrated circuit device until exposing said plurality of metallized trenches therein, whereby electrical contact to the active layer of said integrated circuit device can be provided via said exposed metallized trenches.

2. The packaging method of claim 1, further comprising the steps of:

(d) providing an additional integrated circuit device having a first surface and a second surface, said additional integrated circuit device having an active layer adjacent said first surface and a substrate adjacent said second surface, said additional integrated circuit device further including a plurality of metallized trenches therein extending from said first surface through said active layer and only partially into said substrate, at least some of said plurality of metallized trenches being in electrical contact with the active layer of said additional integrated circuit device;

(e) affixing said additional integrated circuit device to the exposed surface of the last thinned integrated circuit device such that said active layer of said additional integrated circuit device and/or said plurality of metallized trenches of said additional integrated circuit device are electrically coupled to at least some of the exposed metallized trenches of the last thinned integrated circuit device, and such that said second surface of said additional integrated circuit device is exposed; and

(f) thinning substrate from the exposed additional integrated circuit device until exposing at least some of said metallized trenches therein, whereby electrical contact to the active layer of said additional integrated circuit device can be provided via said exposed metallized trenches.

3. The packaging method of claim 2, further comprising the step of repeating said steps (d)-(f) a plurality of times such that said multi-device package includes a plurality of electrically interconnected, thinned integrated circuit devices therein.

4. The packaging method of claim 2, wherein prior to said affixing step (e) said method further comprises the step of:

(g) metallizing the exposed surface of the last thinned integrated circuit device so as to electrically connect to at least some of said exposed metallized trenches in said substrate, said exposed surface metallization including forming interconnection pads on said insulating layer for facilitating electrical connection between the metallized trenches of said thinned integrated circuit device and said additional integrated circuit device provided in step (d).

5. The packaging method of claim 4, further comprising the step of repeating steps (d)-(g) a plurality of times such that said multichip package includes a plurality of electrically interconnected, thinned integrated circuit devices therein.

6. The packaging method of claim 3, wherein each of said integrated circuit device affixing steps (e) includes adhesively bonding said additional integrated circuit device to the last thinned integrated circuit device in the package.

7. The packaging method of claim 3, wherein said integrated circuit devices each comprise a semiconductor wafer having multiple integrated circuits thereon, and said method further includes the step of dicing said multiple wafer package into separate multichip packages.

8. The packaging method of claim 1, wherein said carrier comprises a base integrated circuit device, said base device having a first surface and a second surface in substantially parallel opposing relation, said base device having an active layer adjacent said first surface and a substrate adjacent said second surface, and wherein said affixing step (b) includes affixing said integrated circuit device of step (a) to said base integrated circuit device such that the active layers of said devices are electrically coupled.

9. The packaging method of claim 1, wherein said providing step (a) further includes the steps of:

forming trenches in said integrated circuit device extending from said first surface through said active layer and only partially into said substrate; and

metallizing said trenches formed in said integrated circuit device.

10. The packaging method of claim 9, wherein before said step of metallizing said trenches, an electrical insulator is formed on sidewalls of said trenches within said substrate.

11. The packaging method of claim 9, wherein said trench forming step includes forming said trenches to be less than thirty micrometers in depth from said first surface of said chip.

12. The packaging method of claim 1, wherein said thinning step (c) includes chemically removing said exposed substrate.

13. The packaging method of claim 12, wherein said thinning step (c) includes mechanically removing said substrate prior to said step of chemically removing substrate from said exposed surface.

14. The packaging method of claim 13, wherein said step of mechanically removing substrate proceeds until said substrate is less than 400 micrometers thick.

15. The packaging method of claim 12, wherein the substrate of said integrated circuit device includes a buried etch stop layer and wherein said thinning step (c) includes chemically removing the exposed substrate until reaching said buried etch stop layer.