High power high frequency metal-semiconductor field-effect transistor formed in silicon carbide

• US 5,270,554 A
• Filed: 06/14/1991
• Issued: 12/14/1993
• Est. Priority Date: 06/14/1991
• Status: Expired due to Term

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: Cree Research, Inc. (Wolfspeed, Inc.)
• Inventors: Palmour, John W.
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US07/715,560
• Time in Patent Office: 914 Days
• Field of Search: 357/15, 357/22, 357/61, 357/55, 357/56, 357/63, 357/64, 357/67, 357/68, 437/100, 257/77, 257/280, 257/284, 257/287, 257/472
• US Class Current: 257/77
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802

Abstract

A high power, high frequency, metal-semiconductor field-effect transistor comprises a bulk single crystal silicon carbide substrate, an optional first epitaxial layer of p-type conductivity silicon carbide formed upon the substrate, and a second epitaxial layer of n-type conductivity silicon carbide formed upon the first epitaxial layer. The second epitaxial layer has two separate well regions therein that are respectively defined by higher carrier concentrations of n-type dopant ions than are present in the remainder of the second epitaxial layer. Ohmic contacts are positioned upon the wells for respectively defining one of the well regions as the source and the other as the drain. A Schottky metal contact is positioned upon a portion of the second epitaxial layer that is between the ohmic contacts and thereby between the source and drain for forming an active channel in the second epitaxial layer when a bias is applied to the Schottky contact.

Claims

1. A high power, high frequency, metal-semiconductor field-effect transistor comprising:

a bulk single crystal silicon carbide substrate;

an n-type epitaxial layer of n-type conductivity silicon carbide upon said substrate,

two separate well regions in said epitaxial layer that are respectively defined by higher n-type carrier concentrations than are present in the remainder of said epitaxial layer;

a p-type epitaxial layer of p-type conductivity silicon carbide between said substrate and said n-type epitaxial layer;

ohmic contacts upon said well regions in said n-type epitaxial layer for respectively defining one of said well regions as the source and the other of said well regions as the drain;

a Schottky metal contact upon a portion of said n-type epitaxial layer that is between said ohmic contacts and thereby between said source and said drain for forming an active channel in said n-type epitaxial layer between said source and said drain when a bias is applied to said Schottky metal contact; and

a conducting plane formed on said substrate opposite said p-type epitaxial layer.

2. A transistor according to claim 1 wherein said substrate is formed of silicon carbide selected from the group consisting of 6H, 4H, 15R or 3C silicon carbide, said n-type epitaxial layer is formed of silicon carbide selected from the group consisting of 6H, 4H, 15R or 3C silicon carbide and said p-type epitaxial layer is formed of silicon carbide selected from the group consisting of 6H, 4H, 15R or 3C silicon carbide.

3. A transistor according to claim 1 wherein the distance from said source to said Schottky metal contact is large enough to prevent the flow of any substantial leakage current from the source to the gate when a bias is applied to the gate while small enough to minimize the effect of the low electron mobility of silicon carbide.

4. A transistor according to claim 1 further comprising an overlayer upon said ohmic contacts and said Schottky metal contact, wherein said overlayer is a metal selected form the group consisting of gold, silver, aluminum, platinum and copper.

5. A transistor according to claim 1 wherein said Schottky metal contact has a width and length that have complimentary dimensions such that the power reflected into said source and said drain contacts is substantially zero when a voltage is applied across said source and said drain contacts and a bias is applied to said Schottky metal contact.

6. A high power, high frequency, metal-semiconductor field-effect transistor comprising:

a bulk single crystal silicon carbide substrate;

a first epitaxial layer of p-type conductivity silicon carbide on said substrate;

a second epitaxial layer of n-type conductivity silicon carbide upon said first epitaxial layer, wherein said epitaxial layers form a mesa having sidewalls extending downward from said second epitaxial layer into said first epitaxial layer which define the periphery of said transistor;

two separate well regions in said second layer that are respectively defined by higher n-type carrier concentrations than are present in the remainder of said second epitaxial layer;

ohmic contacts upon said well regions in said second epitaxial layer for respectively defining one of said well regions as the source and the other of said well regions as the drain; and

a Schottky metal contact upon a portion of said second epitaxial layer that is between said ohmic contacts and thereby between said source and said drain for forming an active channel in said second epitaxial layer between said source and said drain when a bias is applied to said Schottky metal contact.

7. A transistor according to claim 6 wherein said substrate is formed of silicon carbide selected from the group of 6H, 4H, 15R or 3C silicon carbide, said first epitaxial layer is formed of silicon carbide selected from the group of 6H, 4H, 15R or 3C silicon carbide and said second epitaxial layer is formed of silicon carbide selected from the group of 6H, 4H, 15R or 3C silicon carbide.

8. A transistor according to claim 6 wherein the distance from said source to said Schottky metal contact is large enough to prevent the flow of any substantial leakage current from the source to the Schottky metal contact when a bias is applied to the Schottky metal contact while small enough to minimize the effect of the low electron mobility of silicon carbide.

9. A transistor according to claim 6 wherein said Schottky metal contact is recessed in said active channel portion of said n-type epitaxial layer.

10. A transistor according to claim 6 wherein said Schottky metal contact is a mushroom gate contact.

11. A transistor according to claim 6 further comprising an overlayer upon said ohmic contacts, wherein said overlayer is a metal selected from the group consisting of gold, silver, aluminum, platinum and copper.

12. A transistor according to claim 6 further comprising an overlayer upon said Schottky metal contact, wherein said overlayer is a metal selected from the group consisting of gold, silver, aluminum, platinum and copper.

13. A transistor according to claim 6 wherein said mesa further comprises said substrate and said sidewalls of said mesa extend downward into said substrate.

14. A transistor according to claim 6 wherein said Schottky metal contact has a width and length that have complimentary dimensions such that the power reflected into said source and said drain contacts is substantially zero when a voltage is applied across said source and said drain contacts and a bias is applied to said Schottky metal contact.

15. A transistor according to claim 6 wherein the length of said Schottky metal contact is less than about 2.0 microns.

16. A transistor according to claim 6 wherein the distance from said source to said Schottky metal contact is about 2.0 microns or less.

17. A transistor according to claim 6, further comprising a conducting plate formed on said substrate opposite said first epitaxial layer.

18. A transistor according to claim 6 wherein the length and width of said Schottky metal contact is selected to minimize reflection of power while operating at frequencies from about 0.5 GHz to about 30 GHz.

19. A transistor according to claim 6 wherein the n-type carrier concentration of said n-type epitaxial layer is from between about 2×

10¹⁶ and 2×

10¹⁸ cm^-3.

20. A transistor according to claim 6 wherein said Schottky metal contact is a mushroom gate comprising:

a first gate layer of metal selected from the group consisting of gold, platinum and platinum silicide contacting said second epitaxial layer; and

an overlayer on said first gate layer of metal and comprising a metal selected from the group consisting of gold, silver, aluminum, platinum and copper.

21. A transistor according to claim 6 wherein said first epitaxial layer comprises semi-insulating silicon carbide.

22. A transistor according to claim 6 wherein said substrate comprises semi-insulating silicon carbide.

23. A transistor according to claim 6 wherein the thickness and carrier concentration of said n-type epitaxial layer is selected to provide a pinch-off voltage of from about -3 volts to about -20 volts.

24. A transistor according to claim 21 wherein said semi-insulating silicon carbide comprises silicon carbide with a deep level dopant incorporated therein.

25. A transistor according to claim 24 wherein said deep level dopant is boron.

26. A transistor according to claim 21 wherein said semi-insulating layer has a resistance of greater than about 10,000 Ω

-cm.

27. A high power, high frequency, metal-semiconductor field-effect transistor comprising:

a bulk crystal silicon carbide substrate;

an epitaxial layer of n-type silicon carbide formed on said substrate;

a pair of mesas of n-type conductivity silicon carbide on said n-type epitaxial layer, said mesas having higher n-type carrier concentrations than said n-type epitaxial layer;

ohmic contacts upon said mesas for respectively defining one of said mesas as the source and the other of said mesas as the drain; and

a Schottky metal contact upon a portion of said epitaxial layer that is between said mesas and thereby between said source and said drain for forming an active channel in said n-type epitaxial layer between said source and said drain when a bias is applied to said Schottky metal contact.

28. A transistor according to claim 27 where said mesas respectively comprise a layer of n⁺ conductivity SiC on said n-type conductivity epitaxial layer.

29. A transistor according to claim 28 wherein said n⁺ conductivity layer is an epitaxial layer.

30. A transistor according to claim 27 where said substrate and said n-type epitaxial layer form a mesa having sidewalls which define the periphery of said transistor, said sidewalls of said mesa extending downward into said substrate.

31. A transistor according to claim 27 wherein said substrate is silicon carbide selected from the group consisting of 6H, 4H, 15R or 3C silicon carbide and said epitaxial layer is silicon carbide selected from the group consisting of 6H, 4H, 15R or 3C silicon carbide.

32. A transistor according to claim 27 wherein the distance from said source to said Schottky metal contact is large enough to prevent the flow of any substantial leakage current from the source to the gate when a bias is applied to the gate while small enough to minimize the effect of the low electron mobility of silicon carbide.

33. A transistor according to claim 27 further comprising a conducting plane on said substrate opposite said epitaxial layer.

34. A high power, high frequency, metal-semiconductor field-effect transistor according to claim 27 wherein said Schottky metal contact has a width and length that have complimentary dimensions such that the power reflected into said source and said drain contacts is substantially zero when a voltage is applied across said source and said drain contacts and a bias voltage is applied to said Schottky metal contact.

35. A transistor according to claim 27 further comprising an overlayer upon said ohmic contacts and said Schottky metal contact, wherein said overlayer is a metal selected from the group consisting of aluminum, silver, gold, platinum and copper.

36. A transistor according to claim 27 wherein said substrate is semi-insulating silicon carbide.

37. A high power, high frequency, metal-semiconductor field-effect transistor comprising:

a bulk crystal silicon carbide substrate;

a first epitaxial layer of p-type conductivity silicon carbide on said substrate;

a second epitaxial layer of n-type silicon carbide on said first epitaxial layer;

a pair of mesas of n-type conductivity silicon carbide on said n-type second epitaxial layer, said mesas having higher n-type carrier concentrations than said n-type second epitaxial layer;

ohmic contacts upon said mesas for respectively defining one of said mesas as the source and the other of said mesas as the drain; and

a Schottky metal contact upon a portion of said second epitaxial layer that is between said mesas and thereby between said source and said drain for forming an active channel in said n-type epitaxial layer between said source and said drain when a bias is applied to said Schottky metal contact.

38. A transistor according to claim 37 where said mesas respectively comprise a layer of n⁺ conductivity SiC on said n-type conductivity epitaxial layer.

39. A transistor according to claim 38 wherein said n⁺ conductivity layer is an epitaxial layer.

40. A transistor according to claim 37 where said substrate and said n-type epitaxial layer form a mesa having sidewalls which define the periphery of said transistor, said sidewalls of said mesa extending downward into said first epitaxial layer.

41. A transistor according to claim 40 where said sidewalls of said mesa extend downward into said substrate.

42. A transistor according to claim 37 wherein said substrate is silicon carbide selected from the group consisting of 6H, 4H, 15R or 3C silicon carbide, said first epitaxial layer is silicon carbide selected from the group consisting of 6H, 4H, 15R or 3C silicon carbide and said second epitaxial layer is silicon carbide selected from the group consisting of 6H, 4H, 15R or 3C silicon carbide.

43. A transistor according to claim 37 wherein the distance from said source to said Schottky metal contact is large enough to prevent the flow of any substantial leakage current from the source to the gate when a bias is applied to the gate while small enough to minimize the effect of the low electron mobility of silicon carbide.

44. A transistor according to claim 37 wherein said Schottky metal contact is recessed in said active channel portion of said second epitaxial layer.

45. A transistor according to claim 37 wherein said source mesa is a retrograde etched mesa.

46. A transistor according to claim 37 further comprising a conducting plate on said substrate opposite said first epitaxial layer.

47. Transistor according to claim 37 wherein said Schottky metal contact has a width and length that have complimentary dimensions such that the power reflected into said source and said drain contacts is substantially zero when a voltage is applied across said source and said drain contacts and a bias voltage is applied to said Schottky metal contact.

48. A transistor according to claim 37 wherein the distance from said source to said Schottky metal contact is about 2.0 microns or less.

49. A transistor according to claim 37 wherein the length of said Schottky metal contact is less than about 2.0 microns.

50. A transistor according to claim 47 wherein the length and width of said Schottky metal contact minimize the reflection of power while operating at frequencies from about 0.5 GHz to about 30 GHz.

51. A transistor according to claim 37 wherein the n-type carrier concentration of said n-type epitaxial layer is from about 2×

10¹⁶ to about 2×

10¹⁸ cm^-3.

52. A transistor according to claim 37 further comprising an overlayer upon said ohmic contacts, said overlayer is a metal selected from the group consisting of aluminum, silver, gold, platinum and copper.

53. A transistor according to claim 37 further comprising an overlayer upon said Schottky metal contact, wherein said overlayer is a metal selected from the group consisting of aluminum, silver, gold, platinum and copper.

54. A transistor according to claim 37 wherein said first epitaxial layer is semi-insulating silicon carbide.

55. A transistor according to claim 37 wherein said substrate is semi-insulating silicon carbide.

56. A transistor according to claim 37 wherein the thickness and carrier concentration of said n-type epitaxial layer is selected to provide a pinch-off voltage of between about -3 volts and -20 volts.

57. A transistor according to claim 54 wherein said semi-insulating silicon carbide is silicon carbide with a deep level dopant incorporated therein.

58. A transistor according to claim 57 wherein said deep level dopant is boron.

59. A transistor according to claim 54 wherein said semi-insulating silicon carbide has a resistivity of greater than about 10,000 Ω

-cm.

60. A high power, high frequency, metal-semiconductor field-effect transistor comprising:

bulk single crystal silicon carbide substrate;

a first epitaxial layer of silicon carbide having a p-type conductivity formed upon said substrate;

a second epitaxial layer of n-type conductivity silicon carbide formed upon said first epitaxial layer,

said second epitaxial layer having a plurality of well regions therein that are respectively defined by higher n-type carrier concentrations than are present in the remainder of said second epitaxial layer;

ohmic contacts upon said plurality of well regions in said second epitaxial layer for alternately electrically connecting said plurality of said well regions defining an alternating plurality of source regions and drain regions;

a plurality of electrically connected Schottky metal contacts for forming a plurality of active channels in said second epitaxial layer between said plurality of source regions and said plurality of drain regions when a bias is applied to said Schottky metal contacts, each of said Schottky metal contacts being formed upon a portion of said second epitaxial layer that is between one of said source regions and one of said drain regions.

61. A high power, high frequency, metal-semiconductor field-effect transistor comprising:

a bulk single crystal silicon carbide substrate;

a first epitaxial layer silicon carbide having a p-type conductivity formed upon said substrate;

a second epitaxial layer of n-type conductivity silicon carbide formed upon said first epitaxial layer,

a plurality of mesas on said second epitaxial layer, said mesas having higher n-type carrier concentrations than are present in said second epitaxial layer;

ohmic contacts upon said plurality of mesas for alternately electrically connecting said plurality of said mesas defining an alternating plurality of source mesas and drains mesas;

a plurality of electrically connected Schottky metal contacts formed upon said second epitaxial layer for forming a plurality of active channels in said second epitaxial layer between said plurality of source mesas and said plurality of drain mesas when a bias is applied to said Schottky metal contacts, each of said plurality of Schottky metal contacts positioned between one of said source mesas and one of said drain mesas.

62. A high power, high frequency, metal-semiconductor field-effect transistor comprising:

a bulk single crystal semi-insulating silicon carbide substrate;

an epitaxial layer of n-type conductivity silicon carbide upon said substrate,

two separate well regions in said epitaxial layer that are respectively defined by higher n-type carrier concentrations than are present in the remainder of said epitaxial layer;

ohmic contacts upon said well regions in said epitaxial layer for respectively defining one of said well regions as the source and the other of said well regions as the drain; and

a Schottky metal contact upon a portion of said epitaxial layer that is between said ohmic contacts and thereby between said source and said drain for forming an active channel in said epitaxial layer between said source and said drain when a bias is applied to said Schottky metal contact.

63. A transistor according to claim 62 wherein said substrate is formed of silicon carbide selected from the group consisting of 6H, 4H, 15R or 3C silicon carbide and said epitaxial layer is formed of silicon carbide selected from the group consisting of 6H, 4H, 15R or 3C silicon carbide.

64. A high power, high frequency, metal-semiconductor field-effect transistor comprising:

a bulk single crystal silicon carbide substrate;

an epitaxial layer of n-type conductivity silicon carbide upon said substrate,

two separate well regions in said epitaxial layer that are respectively defined by higher n-type carrier concentrations than are present in the remainder of said epitaxial layer;

ohmic contacts upon said well regions in said epitaxial layer for respectively defining one of said well regions as the source and the other of said well regions as the drain;

a Schottky metal contact upon a portion of said epitaxial layer that is between said ohmic contacts and thereby between said source and said drain for forming an active channel in said epitaxial layer between said source and said drain when a bias is applied to said Schottky metal contact; and

a conducting plane formed on said substrate opposite said epitaxial layer.

65. A transistor according to claim 64 wherein said substrate is formed of silicon carbide selected from the group consisting of 6H, 4H, 15R or 3C silicon carbide and said epitaxial layer is formed of silicon carbide selected from the group consisting of 6H, 4H, 15R or 3C silicon carbide.

66. A high power, high frequency, metal-semiconductor field-effect transistor comprising:

a bulk single crystal silicon carbide substrate;

an epitaxial layer of n-type conductivity silicon carbide upon said substrate, wherein said substrate and said epitaxial layer form a mesa having sidewalls extending downward from said epitaxial layer into said substrate which define the periphery of said transistor;

two separate well regions in said epitaxial layer that are respectively defined by higher n-type carrier concentrations than are present in the remainder of said epitaxial layer;

ohmic contacts upon said well regions in said epitaxial layer for respectively defining one of said well regions as the source and the other of said well regions as the drain;

a Schottky metal contact upon a portion of said epitaxial layer that is between said ohmic contacts and thereby between said source and said drain for forming an active channel in said epitaxial layer between said source and said drain when a bias is applied to said Schottky metal contact; and

a conducting plane formed on said substrate opposite said epitaxial layer.

67. A transistor according to claim 66 wherein said substrate is formed of silicon carbide selected from the group consisting of 6H, 4H, 15R or 3C silicon carbide and said epitaxial layer is formed of silicon carbide selected from the group consisting of 6H, 4H, 15R or 3C silicon carbide.