Electro-static discharge protection circuit with bimodal resistance characteristics

• US 5,270,565 A
• Filed: 05/30/1991
• Issued: 12/14/1993
• Est. Priority Date: 05/12/1989
• Status: Expired due to Term

• Current Assignee: Western Digital Corporation
• Original Assignee: Western Digital Corporation
• Inventors: Lee, Alan, Ouyang, Kenneth W., Marmet, Melvin L., Lee, Kwok Fai V.
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US07/708,790
• Time in Patent Office: 929 Days
• Field of Search: 357/23.13, 357/51, 257/355, 257/356, 257/358, 257/360, 257/363
• US Class Current: 257/358
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

An electrostatic discharge protection circuit employing an extended resistive structure having bimodal resistance characteristics in series with an input/output buffer circuit and an input/output electrical contact pad on an integrated circuit. The extended resistive structure is integrally formed with the device or devices in the buffer circuit most susceptible to damage due to ESD breakdown effects In a first resistance mode during normal circuit operations, the resistor has a low resistance value and introduces virtually no additional load to the input/output buffer circuitry. In a second mode of operation during ESD discharge, the resistor has a second significantly higher resistance which reduces current values during the ESD event thereby protecting the buffer circuit. Thick oxide snap-back device is also employed to provide a parallel ESD discharge path with low power dissipation.

Claims

1. An electronic discharge protection circuit integrated in a CMOS integrated circuit chip having a substrate and an electrical contact pad, comprising:

a first region of a p conductivity type semiconductor material formed in said substrate;

a single field effect transistor formed in said first region, said field effect transistor having highly doped source and drain regions of said n conductivity type formed at spaced apart locations in said first region and a channel region formed by the portion of said p conductivity type first region between said spaced apart source and drain regions, wherein one of said source or drain regions is positioned adjacent said well region and extends partially into said well region, wherein said field effect transistor is subject to breakdown conduction in response to externally generated voltage surges applied to said pad;

a well region of an n conductivity type semiconductor material formed in said substrate adjacent said first region and having a resistively to current flowing from said pad to said field effect transistor that increases upon breakdown of said field effect transistor; and

wherein said well region is electrically coupled to said contact pad at a position spaced apart from sad first region.

2. An electrostatic discharge protection circuit as set out in claim 1, further comprising an n+ contact region formed in said well region, and wherein said contact pad is electrically coupled to said n+ contact region.

3. An electrostatic discharge protection circuit as set out in claim 2, further comprising:

a second well region of said p conductivity type semiconductor material positioned adjacent said well region and spaced apart from sad first region; and

a snap-back device comprising a snap-back source region and a snap-back drain region of said n conductivity type semiconductor material spaced apart to form a channel region of said p conductivity type second region, and a thick oxide layer formed over said channel region to absorb hot carriers created during snap-back operation of said snap-back device, wherein said snap-back device region is coupled to said contact pad and said snap-back source region is coupled to ground potential.

4. An improved integrated circuit, comprising:

a substrate of a first conductivity type semiconductor material having an upper major surface;

an electrical contact pad formed on said upper major surface of said substrate;

a single field effect transistor formed on said upper major surface of said substrate, said field effect transistor having a source region, a channel region and a drain region formed in said substrate, wherein said source and drain regions are spaced apart highly doped regions of a second conductivity type formed in said substrate and wherein said channel region has a length defined by the spacing between the source region and the drain region, and wherein said source, drain and channel regions have a width dimension substantially grater than the channel length, and wherein said field effect transistor is subject to breakdown conduction in response to externally generated voltage surges applied to said pad;

a lightly doped region of said second conductivity type formed adjacent said field effect transistor and having an extended contact region with said field effect transistor along said width dimension and having a resistively to current flowing from said pad to said field effect transistor that increases upon breakdown of said field effect transistor;

a highly doped contact region of said second conductivity type formed on said upper major surface of said substrate, spaced apart from said field effect transistor by said lightly doped region; and

conductive means, electrically coupled to said highly doped contact region and said pad, for providing an electrical contact therebetween.

5. An integrated circuit as set out in claim 4, wherein said second conductivity type is n type doped silicon.

6. An integrated circuit as set out in claim 4, wherein said second conductivity type is p type doped silicon.

7. An integrated circuit as set out in claim 5, wherein said lightly doped region is doped with phosphorus at a concentration of approximately 10¹⁵ atoms/cc.

8. An integrated circuit as set out in claim 5, wherein said highly doped regions of said second conductivity type are doped with As atoms at approximately 10¹⁹ atoms/cc.

9. An integrated circuit as set out in claim 8, wherein said width dimension is approximately 100-3,000 microns and said channel length is approximately 0.5-2 microns.

10. An improved integrated circuit device comprising:

a substrate of a first conductivity type semiconductor material having an upper major surface;

an electrical contact pad formed on said upper major surface of said substrate;

a single field effect transistor formed on said upper major surface of said substrate, said field effect transistor having a source region, a channel region and a drain region formed in said substrate and a gate oxide layer formed over said channel region, wherein said source and drain regions are spaced apart highly doped substrate and wherein said channel region has a length defined by the spacing between the source region and the drain region, and wherein said channel length is less than 2 microns and said gate oxide thickness is less than 275 Å and

wherein said field effect transistor has a width perpendicular to the length of said channel region, and wherein said field effect transitory is subject to breakdown conduction in response to externally generated voltage surges applied to said pad;

a lightly doped region of said second conductivity type formed adjacent said field effect transistor and having an extended contact region with said field effect transistor along the width dimension and having a resistively to current flowing from said pad to sad field effect transistor that increases upon breakdown of said field effect transistor;

a highly doped contact region of said second conductivity type formed on said upper major surface of said substrate, spaced apart from said field effect transistor by said lightly doped region; and

conductive means, electrically coupled to said highly doped contact region and said pad, for providing an electrical contact therebetween.

11. An integrated circuit device as set out in claim 10, wherein said second conductivity type is n type doped silicon.

12. An integrated circuit device as set out in claim 10, wherein said second conductivity type is p type doped silicon.

13. An integrated circuit device as set out in claim 10, further comprising a second field effect transistor formed on said upper major surface of said substrate and having spaced apart source and drain regions of said first conductivity type and a channel region of said second conductivity type, wherein said source region is coupled to a reference potential and said drain region is coupled to the drain of the first field effect transistor and said pad.