Refreshing ferroelectric capacitors

• US 5,270,967 A
• Filed: 01/16/1991
• Issued: 12/14/1993
• Est. Priority Date: 01/16/1991
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Moazzami, Reza, Jaffe, James M.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): GLEMBOCKI, CHRISTOPHE
• Application Number:
  US07/642,022
• Time in Patent Office: 1,063 Days
• Field of Search: 365/117, 365/145, 365/222, 365/230.06
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/223 using MOS with ferroelectric gate insulating film

Abstract

The endurance of ferroelectric capacitors can be extended by refreshing the ferroelectric material. The ferroelectric material is refreshed by impressing a voltage across the ferroelectric capacitor, which voltage is higher than that which the capacitor experiences during normal operation. A memory array having ferroelectric capacitive cells can be refreshed by first reading the memory cells, temporarily storing the data in associated sense amplifiers, refreshing the memory cells by impressing a higher-than-normal voltage across the ferroelectric cell capacitors, then rewriting the temporarily stored data back into the memory cells. Refresh circuits connected between the drive line and bit line common to a number of cells are driven with voltages which are higher than the memory cell experiences during normal read operations. A V_cc to ground pulse train is applied to the drive line, while an inverted waveform thereof is applied to the bit line during refresh operations.

Claims

1. In a nonvolatile memory cell having a ferroelectric capacitor, a switching transistor, a word line, a bit line and a drive line, a method for extending an endurance of the ferroelectric capacitor, comprising the steps of:

accessing the memory cell by addressing the word line;

causing a read voltage of a first magnitude to be applied across the ferroelectric capacitor to read the memory cell with respect to a polarization state; and

carrying out at least one cycle including the steps of applying a refresh voltage to a second magnitude greater than the read voltage of the first magnitude and of one polarity across the ferroelectric capacitor to revitalize a ferroelectric material thereof, and applying the refresh voltage of the second magnitude and of a polarity opposite said one polarity across the ferroelectric capacitor to refresh the ferroelectric capacitor and revitalize the ferroelectric material thereof.

2. The method of claim 1, further including driving the drive line during said cycle with the refresh voltage and maintaining the bit line at a circuit common voltage.

3. The method of claim 2, further including maintaining the drive line during a different portion of the cycle at a circuit common voltage and increasing the bit line voltage to said refresh voltage of the second magnitude.

4. The method of claim 1, further including counting the number of memory read and write access cycles to which the memory cell has been subjected, and on a predefined count, initiating said refresh of said ferroelectric capacitor.

5. The method of claim 1, further including carrying out a plurality of said cycles to define a single refresh operation for said memory cell, and waiting a predefined period of time after one refresh operation before initiating a subsequent refresh operation.

6. The method of claim 5, further including waiting nonuniform periods of time between said refresh operations.

7. The method of claim 5, further including periodically refreshing the memory cell in a manner such that the time periods become shorter between refresh operations.

8. The method of claim 1, further including applying a supply voltage of about 5 volts to a device having said cell incorporated therein, and reading the cell by applying approximately 2-3 volts across the ferroelectric capacitor, and refreshing the cell by applying approximately 5 volts across the ferroelectric capacitor.

9. The method of claim 1, wherein a semiconductor chip includes an array of said ferroelectric capacitor cells, and wherein said refresh is carried out by increasing a supply voltage to said chip.

10. The method of claim 1, further including during each said refresh cycle, subjecting the ferroelectric capacitor to a plurality of pulses, each of which has a magnitude corresponding to said second magnitude.

11. A circuit for carrying out the method of claim 1.

12. A method of extending the endurance of a memory array having a number of addressable nonvolatile memory cells, each memory cell having a ferroelectric capacitor connectable between a drive line and a bit line, comprising the steps of:

a) accessing a memory cell of the array to revitalize a ferroelectric capacitor by applying an address to a word line associated with the memory cell to connect the ferroelectric capacitor between the drive line and the bit line;

b) reading the memory cell by applying a read voltage across the ferroelectric capacitor of the accessed memory cell;

c) isolating the bit line from a sense amplifier;

d) when the bit line is isolated from sense amplifier, revitalizing the ferroelectric capacitor of the accessed memory cell by applying a voltage greater than the read voltage across the ferroelectric capacitor via the drive line and the bit line to revitalize the ferroelectric capacitor material; and

e) periodically revitalizing the ferroelectric capacitors of the other memory cells of the array by sequentially repeating steps b) through d).

13. The method of claim 12, further including revitalizing the array by initiating a memory read of the memory cells of the array.

14. The method of claim 12, further including:

reading the memory cell and temporarily storing associated data in the sense amplifier before carrying out the isolation step;

revitalizing the memory cell;

connecting the sense amplifier to the revitalized bit line; and

rewriting the temporarily stored data back into the memory cell.

15. The method of claim 12, further including maintaining the bit line voltage constant and increasing the drive line voltage to said refresh voltage during said revitalizing.

16. The method of claim 12, further including increasing the voltage across the ferroelectric capacitor to a magnitude of at about 50% greater than the magnitude of the read voltage impressed across the capacitors during a read cycle.

17. The method of claim 12, further including applying a voltage of about Vcc/2 to the ferroelectric capacitor of the memory cell during a normal read operation, and applying a voltage of about Vcc across the ferroelectric capacitor during a refresh cycle.

18. The method of claim 17, wherein said array includes row and columns of cells, and further including sequentially refreshing each row of cells during a respective single refresh cycle.

19. Circuits for carrying out the method of claim 12.

20. A ferroelectric memory array powered by a DC supply voltage, comprising:

an array of memory cells, each cell including a ferroelectric capacitive element;

circuits for accessing the array to address at least one memory cell;

a voltage drive circuit for applying a voltage of a first magnitude across the ferroelectric capacitive element of the addressed memory cell during a normal memory read/write operation; and

means for applying a second voltage of a magnitude greater than said first magnitude across the capacitive element of each addressed memory cell during a first refresh operation without increasing said DC supply voltage to revitalize ferroelectric material of the capacitive elements.

21. The memory array of claim 20, wherein said means for applying drives the capacitive element with the second voltage to refresh the ferroelectric material of the capacitor during said first refresh operation that is subsequent to a memory read operation.

22. The memory array of claim 20, further including a counter for counting a number of memory read and write access cycles, and means responsive to a predetermined count for causing the first refresh operation to be initiated.

23. The memory array of claim 22, wherein said counter is formed on a semiconductor chip with said array.

24. The memory array of claim 22, wherein said counter has plural stages that are nonvolatile, and other less significant bit counter stages that are volatile.

25. The memory array of claim 22, wherein said memory array is formed on a silicon chip, and said counter is located off said chip.

26. The memory array of claim 20, wherein said array is formed on a semiconductor chip supplied with a supply voltage defined as V_cc, and means for increasing the supply voltage during a refresh operation occurring subsequent to the first refresh operation.

27. The memory array of claim 20, further including a common drive line circuit for applying a voltage to a number of ferroelectric capacitive elements of respective cells connected to a common drive line, and a circuit associated with said common drive line circuit for driving the common drive line with a voltage of a first magnitude for read operations, and for driving the common drive line with a voltage of a second magnitude greater than the first magnitude during said refresh operation.

28. The memory array of claim 20, further including a sense amplifier associated with a bit line to which said memory cells are connected, said sense amplifier having a voltage drive circuit for driving said bit line with a first voltage during normal memory operations, and for driving the bit line with said higher voltage during said refresh operation.

29. The memory array of claim 20, further including a drive circuit for applying a refresh voltage directly across each ferroelectric capacitive element.

30. The memory array of claim 20, wherein said drive circuit is connected across a drive line and a bit line each common to plural memory cells of the array.

31. The memory array of claim 30, wherein said drive circuit includes a CMOS transistor pair having a common node connected to the drive line, and another CMOS transistor pair having a common node connected to the bit line.

32. The memory array of claim 31, further including an inverter for inverting a drive signal before being applied to one of said CMOS transistor pairs to provide out of phase signals for driving the drive line and the bit line.

33. A ferroelectric memory array, comprising:

an array of nonvolatile memory cells, each memory cell including a ferroelectric capacitive element;

circuits for accessing word lines of the array to address at least one memory cell;

a bit line common to a number of memory cells for transferring electrical charge thereto from the ferroelectric capacitive elements of the respective addressed memory cells;

a drive line common to a number of memory cells for applying a drive voltage to ferroelectric capacitive elements; and

a drive circuit comprising a bit line drive circuit and a drive line drive circuit connected respectfully to said bit line and to said drive line for applying a bit line refresh voltage and a drive line refresh voltage directly across the ferroelectric capacitive element of at least one memory cell associated with the drive line and the bit line, said bit line and drive line refresh voltage being greater in amplitude than that applied across the ferroelectric capacitive elements during normal read/write operations.

34. The ferroelectric memory array of claim 33, wherein during a normal memory cell access the accessed memory cell is configured to distribute electrical charge between the ferroelectric capacitive element and capacitance of the bit line so that the resultant voltage across the ferroelectric capacitive element is always less than V, and during a refresh operation a voltage of at least V is applied across the drive line and the bit line.

35. The ferroelectric memory array of claim 33, further including an oscillator for applying a plurality of refresh voltage pulses to the accessed ferroelectric capacitive element during a refresh operation.

36. The ferroelectric memory array of claim 33, further including a counter for totalizing a number of accesses to the array, and a decoder for decoding a predefined count of said counter, an output of said decoder being operative to initiate a refresh operation.

37. The ferroelectric memory array of claim 36, further including means for presetting the counter to a predefined count.

38. The ferroelectric memory array of claim 33, further including a sense amplifier distinct from said bit line drive circuit.

39. The ferroelectric memory array of claim 38, further including a transistor for coupling the bit line to the sense amplifier, said transistor preventing a full supply voltage from being applied across the ferroelectric capacitive elements during normal read and write operations, and wherein said transistor is placed in a nonconductive state during the application of the drive line and bit line refresh voltages.

40. A method of refreshing cells of a ferroelectric memory chip, comprising the steps of:

increasing a supply voltage connected to a pin of said chip from a first magnitude from which the chip normally operates in read and write operations to a second, greater magnitude; and

accessing each cell of the array with said increased magnitude voltage applied to the chip to refresh the ferroelectric material of each cell.

41. The method of claim 40, wherein said accessing step is carried out by reading each memory cell.

42. The method of claim 40, wherein said supply voltage is increased by increasing a positive supply voltage.

43. The method of claim 40, wherein said supply voltage is increased by increasing a negative supply voltage.

44. A ferroelectric memory, comprising:

a plurality of nonvolatile memory cells, each having a ferroelectric capacitive element;

at least one bit line and at least one word line connected to at least one said cell;

at least one drive line connected to said one cell;

a sense amplifier;

an isolation transistor for switchably connecting said bit line to said sense amplifier during reading of the cell, and for isolating the bit line from the sense amplifier during revitalization of the ferroelectric capacitive element of the cell; and

a drive circuit operative during refreshing of the cells for applying a voltage between the drive line and the bit line to revitalize the ferroelectric capacitive element of said one cell.

45. The memory of claim 44, further including an oscillator for driving the drive circuit.

46. The memory of claim 44, further including a counter for totalizing memory accesses, and for initiating a revitalization of the ferroelectric capacitive element after a predetermined number of accesses.

47. The memory of claim 44, wherein said drive circuit includes a first CMOS transistor pair having a common node connected to the drive line and a second CMOS transistor pair having a common node connected to the bit line.

48. The memory of claim 47, wherein each said CMOS transistor pair is connected in series between a supply voltage of said memory and a circuit common of said memory.

49. In a memory cell having a ferroelectric capacitor, a switching transistor, a word line, a bit line and a drive line, a method for extending an endurance of the ferroelectric capacitor, comprising the steps of:

accessing the memory cell by addressing the word line;

causing a voltage of a first magnitude to be applied across the ferroelectric capacitor to read or write the memory cell with respect to a polarization state;

counting the number of memory access cycles to which the memory cell has been subjected, and on a predefined count, initiating a refresh operation;

carrying out the refresh operation by applying a voltage of a second magnitude greater than the first magnitude across the ferroelectric capacitor to refresh the ferroelectric material of said capacitor; and

refreshing the cell with increased magnitudes of refresh voltage at each subsequent refresh operation.