Method for optimum erasing of EEPROM
First Claim
1. For an array of a plurality of electrically erasable and programmable read only memory cells, each cell capable of being programmed to a "programmed" state or erased to an "erased" state, said array capable of undergoing a plurality of program and erase cycles, a method of maintaining uniform program and erase history among a group of cells of the array, comprising the steps of:
- providing a first data encoding where first and second logical states of data are represented respectively by the "erased" state and the "programmed" state, and a second data encoding where the representations of first and second logical states are reversed relative to the "programmed" and "erased" states;
programming the cells of the group with either first or second data encoding randomly in subsequent programming operations of the group, thereby allowing all cells of the group to experience substantially similar programming histories.
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Abstract
Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM). An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses. Techniques include a 2-phase verification process interleaving between pulse applications; special handling of a sample of cells within each erasable unit group; defects handling; adaptive initial erasing voltages; and single-and hybrid-phase algorithms with sector to sector estimation of erase characteristics by table lookup. Techniques are also employed for controlling the uniformity of program/erase cycling of cells in each erasable unit group. Defects handling includes an adaptive data encoding scheme.
485 Citations
20 Claims
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1. For an array of a plurality of electrically erasable and programmable read only memory cells, each cell capable of being programmed to a "programmed" state or erased to an "erased" state, said array capable of undergoing a plurality of program and erase cycles, a method of maintaining uniform program and erase history among a group of cells of the array, comprising the steps of:
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providing a first data encoding where first and second logical states of data are represented respectively by the "erased" state and the "programmed" state, and a second data encoding where the representations of first and second logical states are reversed relative to the "programmed" and "erased" states; programming the cells of the group with either first or second data encoding randomly in subsequent programming operations of the group, thereby allowing all cells of the group to experience substantially similar programming histories. - View Dependent Claims (2)
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3. For an array of a plurality of electrically erasable and programmable read only memory cells, each cell capable of being programmed to a "programmed" state or erased to an "erased" state, said array capable of undergoing a plurality of program and erase cycles, a method of maintaining uniform program and erase history among a group of cells of the array, comprising the steps of:
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providing a first data encoding where first and second logical states of data are represented respectively by the "erased" state and the "programmed" state, and a second data encoding where the representations of first and second logical states are reversed relative to the "programmed" and "erased" states; programming the cells of the group with first or second data encoding in a predetermined sequence in subsequent programming operations of the group, thereby allowing all cells of the group to experience substantially similar programming histories. - View Dependent Claims (4)
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5. For an array of a plurality of electrically erasable and programmable read only memory cells having means for addressing the cells to program, read and erase their states, each cell having a field effect transistor that includes a floating gate and an erase gate, and having a natural threshold voltage that is alterable by programming or erasing to a level of charge on the floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, said array being partitioned into sectors of memory cells, each sector being addressable for simultaneous erasing of all cells therein, a method of erasing a sector of addressed cells of the array, comprising the steps of:
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in a first phase, pulsing an addressed sector with an erase voltage incremented successively from an initial erase voltage and verifying a sample of cells of the addressed sector in between pulses until more than a predetermined number of cells in the addressed sectors are completely erased; and
thereafterin a second phase, continuing pulsing the addressed sector with an erase voltage incremented from the last pulsing step and verifying all cells therein in between pulses until they are completely erased. - View Dependent Claims (6, 7, 8, 9, 10, 11)
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12. For an array of a plurality of electrically erasable and programmable read only memory cells, said array being partitioned into sectors of memory cells, each sector being addressable for simultaneous erasing of all cells therein and capable of undergoing a plurality of program and erase cycles, a method of erasing a sector of addressed cells of the array, comprising the steps of:
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generating a statistical table of optimum erase parameters for a range of sectors which have undergone different program/erase cyclings; storing the number of program/erase cycles (or "cycle count") a sector has undergone as the sector is being program/erase cycled during use of the memory array; reading the cycle count of a sector to be erased; looking up the optimum erase parameters from the statistical table for that cycle count; and erasing the sector with said looked-up optimum erase parameters. - View Dependent Claims (13, 14, 15, 16)
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17. For an array of a plurality of electrically erasable and programmable read only memory cells, each cell capable of being programmed to a "programmed" state or erased to an "erased" state, said array capable of undergoing a plurality of program and erase cycles, a method of programming the cells of the array in spite of non-erasable defective cells thereamong which cannot be erased to an "erased" state, comprising the steps of:
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partitioning the array into a plurality of blocks of cells; providing a first data encoding where first and second logical states of data are represented respectively by the "erased" state and the "programmed" state, and a second data encoding where the representations of first and second logical states are reversed relatively to the "programmed" and "erased" states; locating any non-erasable defective cell among a block of cells for which a corresponding block of data bits is to be written; programming the block of cells with the block of data bits using either first or second data encoding such that the data bit corresponding to the defective cell is caused to be in the "programmed" state, through the appropriate selection of said first or second data encoding. - View Dependent Claims (18)
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19. For an array of a plurality of electrically erasable and programmable read only memory cells, each cell capable of being programmed to a "programmed" state or erased to an "erased" state, said array capable of undergoing a plurality of program and erase cycles, a method of programming the cells of the array in spite of non-programmable defective cells thereamong which cannot be programmed to an "programmed" state, comprising the steps of:
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partitioning the array into a plurality of blocks of cells; providing a first data encoding where first and second logical states of data are represented respectively by the "erased" state and the "programmed" state, and a second data encoding where the representations of first and second logical states are reversed relatively to the "programmed" and "erased" states; locating any non-programmable defective cell among a block of cells for which a corresponding block of data bits is to be written; programming the block of cells with the block of data bits using either first or second data encoding such that the data bit corresponding to the defective cell is caused to be in the "erased" state, through the appropriate selection of said first or second data encoding. - View Dependent Claims (20)
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Specification