Method and apparatus for QPR carrier recovery

• US 5,271,041 A
• Filed: 03/16/1992
• Issued: 12/14/1993
• Est. Priority Date: 03/16/1992
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Scientific-Atlanta Incorporated (Cisco Systems, Inc.)
• Inventors: Montreuil, Leo
• Primary Examiner(s): Kuntz, Curtis
• Assistant Examiner(s): Phan, Hai H.
• Application Number:
  US07/852,277
• Time in Patent Office: 638 Days
• Field of Search: 375/97, 375/80, 375/39, 375/79, 455/255, 455/257, 455/258, 455/259, 455/260, 455/208, 455/210, 455/192.1, 455/192.2
• US Class Current: 375/344
• CPC Class Codes: H04L 25/497 by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343

Abstract

A digital audio communication system includes a digital modulation and demodulation scheme which efficiently uses the bandwidth and channel spacing of a cable television system. A 30 channel digital bit stream is demultiplexed into six groups of five channels. Each group of channels thereafter modulates a carrier by a quadrature partial response (QPR) process. The QPR signal, an amplitude modulated, double sideband, carrier suppressed (AM DSBSC) signal, is then transmitted over the cable system to a multiplicity of subscribers, each of which has a QPR demodulator. The demodulators are of the decision feedback type having a modified Costas loop carrier recovery circuit. The grouping of an odd number (five) of digital audio channels per QPR modulator minimizes error propagation due to the correlative QPR demodulation process. The decision feedback decoding is implemented in simple current nodes where a bilevel output from the decoded data is subtracted from a tertiary level output of a mixer. The resulting bilevel current is converted to a voltage, filtered, and limited to produce a logic output level. The modified Costas loop provides an error voltage based upon the difference of the received data states versus the nominal data states and the quadrant the data occupies. The error voltage is generated by differencing the outputs of two analog switches which have as their inputs analog signals representative of the amplitude level of the data and its inverse of one phase. The sign of the data bit of the opposite phase is used to control the switch and thus select which signal is used.

Claims

1. A carrier recovery circuit for generating the inphase and quadrature phases of a demodulation carrier coherent with the carrier of a quadrature partial response (QPR) signal of the form M_i * sin (ω

_c t)+M_q (t) * cos (ω

_c t), where M_i (t) and M_q (t) are encoded partial response information modulations of the inphase and quadrature phases of a carrier of angular frequency [(ω

_c t)]ω

_c, said carrier recovery circuit comprising;

means for generating analog signals representing the demodulated values of the information signal M_i (t) and its inverse *M_i (t);

means for generating analog signals representing the demodulated values of the information signal M_q (t) and its inverse *M_q (t);

means for generating an error signal based on a selected combination of a analog signals M_i (t), *M_i (t) and the analog signals M_q, *M_q ;

means for generating a variable frequency carrier signal in response to a control signal;

means for generating said control signal in response to said error signal which varies the frequency of said variable frequency carrier signal to minimize the error signal;

means for splitting said variable frequency carrier signal into an inphase phase path and a quadrature phase path; and

means located in said quadrature phase path for shifting the variable frequency carrier signal at least 90°

inphase.

2. A carrier recovery circuit as set forth in claim 1 wherein said error signal generating means includes;

means for generating a digital signal indicative of the demodulated value of M_i (t);

means for generating a digital signal indicative of the demodulated value of M_q (t);

means for selecting the analog signal M_i (t) or its inverse *M_i (t) depending upon the digital logic state of the digital signal M_q (t);

means for selecting the analog signal M_q (t) or its inverse *M_q (t) depending upon the digital logic state of the digital signal M_i (t); and

means for generating said error signal based upon the difference of the selected analog signals.

3. A carrier recovery circuit as defined in claim 2 wherein said means for generating a digital signal indicative of the demodulated value of M_i (t) comprises:

a differential amplifier having an inverting input, a noninverting input, and a logic level output;

wherein the analog signal M_i (t) is coupled to one of said inverting and noninverting inputs and its inverse *M_i (t) is coupled to the other of said inverting and noninverting inputs.

4. A carrier recovery circuit as defied in claim 2 wherein said means for generating a digital signal indicative of the demodulated value of M_q (t) comprises:

a differential amplifier having an inverting input, a noninverting input, and a logic level output; and

wherein the analog signal M_q (t) is coupled to one of said inverting and noninverting inputs and its inverse *M_q (t) is coupled to the other of said inverting and noninverting inputs.

5. A carrier recovery circuit as set forth in claim 2 wherein said means for selecting the analog signal M_i (t) or its inverse *M_i (t) comprises:

an analog multiplexer including first and second analog inputs which can be selectively switched to an analog output based upon the state of a digital signal applied to a selection input;

said analog signal M_i (t) being coupled to one of said first and second inputs and said analog signal *M_i (t) being coupled to the other of said first and second inputs; and

said digital signal M_q (t) being coupled to the selection input.

6. A carrier recovery circuit as set forth in claim 2 wherein said means for selecting the analog signal M_q (t) or its inverse *M_q (t) comprises:

an analog multiplexer including first and second analog inputs which can be selectively switched to an analog output based upon the state of a digital signal applied to a selection input;

said analog signal M_q (t) being coupled to one of said first and second inputs and said analog signal *M_q (t) being coupled to the other of said first and second inputs; and

said digital signal M_i (t) being coupled to the selection input.

7. A carrier recovery circuit as set forth in claim 2 wherein said means for selecting the analog signal M_i (t) or its inverse *M_i (t) and said means for selecting the analog signal M_q (t) or its inverse *M_q (t) comprises:

a first analog multiplier including first and second analog inputs which can be selectively switched to an analog output based upon the state of a digital signal applied to a selection input;

said analog signal M_i (t) being coupled to one of said first and second inputs of said first multiplexer and said analog signal *M_i (t) being coupled to the other of said first and second inputs of said first multiplexer;

said digital signal M_q (t) being coupled to the selection input of said first multiplexer;

a second analog multiplexer including first and second analog inputs which can be selectively switched to an analog output based upon the state of a digital signal applied to a selection input;

said analog signal M_q (t) being coupled to one of said first and second inputs of the second multiplexer and said analog signal *M_q (t) being coupled to the other of said first and second inputs of the second multiplexer; and

said digital signal M_i (t) being coupled to the selection input of the second multiplexer.

8. A carrier recovery circuit as set forth in claim 7 wherein:

said first multiplexer and said second multiplexer are combined in a single multiplexer with four analog inputs, two analog outputs and two digital selection inputs.

9. A carrier recovery circuit as set forth in claim 8 wherein said means for selecting the analog signal M_i (t) or its inverse *M_i (t) includes:

means for selecting the analog signal *M_i (t), if M_q (t) is a logical one, and selecting the analog signal M_i (t), if M_q (t) is a logical zero.

10. A carrier recovery circuit as set forth in claim 8 wherein said means for selecting the analog signal M_q (t) or its inverse *M_q (t) includes:

means for selecting the analog signal *M_q (t), if M_i (t) is a logical one, and selecting the analog signal M_q (t), if M_i (t) is a logical zero.

11. A carrier recovery circuit as set forth in claim 1 wherein said error signal generating means includes:

means for selecting a combination of said analog signals which identify a quadrant of the demodulated signal values of said QPR signal.

12. A carrier recovery circuit as set forth in claim 11 wherein said error signal generating means further includes:

means for selecting a combination of said analog signals which includes one analog signal from the inphase I portion of the QPR signal and one analog signal from the quadrature phase Q portion of the QPR signal.

13. A carrier recovery circuit as set forth in claim 12 wherein said error signal generating means includes:

means for selecting a combination of said analog signals which indicates the amount of phase error in said demodulation carrier.

14. A carrier recovery circuit as set forth in claim 13 wherein said error generating means includes:

means for selecting a combination of said analog signals which indicates whether the phase error in said demodulation carrier is positive phase error or negative phase error.