Method for fabricating diodes for electrostatic discharge protection and voltage references

• US 5,272,097 A
• Filed: 04/07/1992
• Issued: 12/21/1993
• Est. Priority Date: 04/07/1992
• Status: Expired due to Term

• Current Assignee: Philip Shiota
• Original Assignee: Philip Shiota
• Inventors: Shiota, Philip
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TSAI, H JEY
• Application Number:
  US07/864,933
• Time in Patent Office: 623 Days
• Field of Search: 437/56, 437/57, 437/58, 437/904, 437/34, 257/357, 257/328, 257/355, 257/356, 257/487, 257/546
• US Class Current: 438/200
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors

Abstract

A novel process is taught for forming diodes simultaneously with the formation of typical prior art LDD MOS devices. The diodes thus formed have low breakdown voltages, making them suitable for use as voltage reference diodes, or diodes for ESD protection.

Claims

1. A method of fabricating a semiconductor structure comprising the steps of:

a) forming within a first bulk region (1103) of a first conductivity type, a lightly doped source/drain region (1111) of a second conductivity type opposite said first conductivity type;

b) forming within a second bulk region (1102) of said second conductivity type, a second conductivity type lightly doped portion (1110) of a first diode region;

c) forming within said second bulk region (1102) a lightly doped source/drain region (1120) of said first conductivity type;

d) forming within said first bulk region (1103) a first conductivity type lightly doped portion (1121) of a first diode region;

e) forming within said first bulk region (1103) a second conductivity type portion (1114) of said first diode region;

f) forming within said first bulk region (1103) a source/drain region (1115) of said second conductivity type;

g) forming within said second bulk region (1102) a second diode region (1116) of said second conductivity type;

h) forming within said first bulk region (1103) a second diode region (1119) of said first conductivity type;

i) forming within said second bulk region (1102) a source/drain region (1118) of said first conductivity type; and

j) forming within said second bulk region (1102) a first conductivity type portion (1117) of said first diode region,

wherein said first bulk region comprises a lightly doped source/drain MOS device and a diode having said second conductivity type portion of said first diode region formed within said first bulk region serving as a first terminal of said diode and said second diode region within said first bulk region serves as a second terminal of said diode, and

wherein said second bulk region comprises a lightly doped source/drain MOS device and a diode having said first conductivity type portion of said first diode region within said second bulk region serving as a first terminal of said diode and said second diode region within said second bulk region serves as a second terminal of said diode.

2. A method as in claim 1, wherein steps a and b are performed simultaneously.

3. A method as in claim 2, wherein steps a and b are performed simultaneously using a blanket implant.

4. A method as in claim 1, wherein steps c and d are performed simultaneously.

5. A method as in claim 1, wherein steps e, f, and g are performed simultaneously.

6. A method as in claim 1, wherein steps h, i, and j are performed simultaneously.

7. A method as in claim 1, wherein one or both of said steps of forming within said bulk region said lightly doped source/drain regions utilizes gate electrodes as a portion of a mask and wherein said steps of forming within said bulk regions said source/drain regions utilize gate electrode sidewall spacers as a portion of a mask, thereby providing said source/drain regions laterally spaced apart from said gate electrode by a lightly doped source/drain region.

8. A method as in claim 3, wherein regions implanted by said blanket implant are over compensated in subsequent doping steps of opposite conductivity type.

9. A method of fabricating a semiconductor structure comprising the steps of:

a) forming within a first bulk region (5103) of a first conductivity type, a lightly doped source/drain region (5111) of a second conductivity type opposite said first conductivity type;

b) forming within one or more second bulk regions (5102) of said second conductivity type, a second conductivity type lightly doped portion (5110) of a first diode region;

c) forming within said first bulk region (5103) a source/drain region (5115) of said second conductivity type;

d) forming within said second bulk regions (5102) a second diode region (5116) of said second conductivity type;

e) forming within said second bulk regions (5102) a source/drain region (5118) of said first conductivity type; and

f) forming within said second bulk regions (5102) a first conductivity type portion (5117) of said first diode region,

wherein said first bulk regions comprise a lightly doped source/drain MOS device, and

wherein said second bulk regions comprise a MOS device and a diode having said first conductivity type portion of said first diode region within said second bulk regions serving as a first terminal of said diode and said second diode region within said second bulk regions serve as a second terminal of said diode.

10. A method as in claim 9, wherein steps a and b are performed simultaneously.

11. A method as in claim 10, wherein steps a and b are performed simultaneously using a blanket implant.

12. A method as in claim 9, wherein steps c and d are performed simultaneously.

13. A method as in claim 9, wherein steps e and f are simultaneously.

14. A method as in claim 9, which further comprises the s of forming within said second bulk regions (5102) a doped source/drain region of said first conductivity type.

15. A method as in claim 14, wherein one or both of said steps of forming within said bulk regions said lightly doped source/drain regions utilizes gate electrodes as a portion of a mask and wherein said steps of forming within said bulk regions said source/drain regions utilize gate electrode sidewall spacers as a portion of a mask, thereby providing said source/drain regions laterally spaced apart from said gate electrode by a lightly doped source/drain region.

16. A method as in claim 11, wherein regions implanted by said blanket implant are over compensated in subsequent doping steps of opposite conductivity type.

17. A method as in claim 9 which further comprises the step of forming within said first bulk region (5103) a first conductivity type well contact.

18. A method as in claim 17 wherein said step of forming said first conductivity well contact is performed simultaneously with said step of forming said source/drain region within said second bulk regions.