Silicon transistor device with silicon-germanium electron gas hetero structure channel

• US 5,272,365 A
• Filed: 05/26/1992
• Issued: 12/21/1993
• Est. Priority Date: 03/29/1990
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakagawa, Akio
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): WALLACE, VALENCIA MARTIN
• Application Number:
  US07/887,667
• Time in Patent Office: 574 Days
• Field of Search: 357/16, 257/12, 257/17, 257/19, 257/20, 257/22, 257/24, 257/190, 257/191, 257/192, 257/194, 257/195, 257/289, 257/327
• US Class Current: 257/194
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/7378 comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/7782 with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A metal oxide semiconductor field effect transistor with heterostructure has a silicon substrate. Heavily-doped source and drain layers which are different in conductivity type from the substrate are spaced apart from each other in the surface portion of the substrate. A gate electrode of polycrystalline silicon is disposed above the substrate, and is electrically insulated from the substrate by a gate insulation layer made of thermal silicon oxide thin film. A silicon germanium layer is laterally provided in a preselected substrate surface section positioned between the source and drain layers. This layer partially overlaps the source and drain layers at both of its end portions, and is thus electrically in contact with these layers. The silicon germanium layer acts as a channel of the transistor.

Claims

1. A semiconductor heterostructure transistor, which comprises:

a substrate body made from silicon substrate of a first conductivity type having a surface;

a source and a drain of a second conductivity type which are spaced apart from each other to define a channel region therebetween in said substrate body;

a gate electrode which is electrically insulated from the channel region and which is at least partially overlying the channel region; and

a silicon-germanium layer arranged below a silicon surface layer of the substrate body to partially extend into and coincide with said source and to partially extend into and coincide with said drain, said silicon-germanium layer having a lateral spatial extent which is limited to the coinciding regions and which essentially consists of a region between said source and said drain and which has first and second end portions that terminate within a corresponding one of said source and said drain.

2. The transistor according to claim 1, which further comprises:

a dielectric film between said gate electrode and said substrate body surface, said film comprising silicon oxide.

3. The transistor according to claim 2, wherein:

said gate electrode comprises a polycrystalline silicon layer.

4. The transistor according to claim 1, wherein:

said gate electrode has edges which are substantially self-aligned with said source and with said drain.

5. The transistor according to claim 1, wherein:

said gate electrode has a length in a direction which is parallel to the silicon-germanium layer and said length to the gate electrode is less than a length between said source and said drain, of said channel region.

6. A semiconductor heterostructure transistor, which comprises:

a substrate body made from silicon of a first type conductivity having a surface;

a source and a drain of a second type conductivity which are spaced apart from each other to define a channel region therebetween in said substrate body;

a gate electrode which is electrically insulated from the channel region and which is at least partially overlying the channel region; and

a dielectric film between said gate electrode and the substrate body surface;

a silicon-germanium layer on the substrate body surface and having a lateral spatial extent which is limited to a region between said source and said drain, said silicon-germanium layer includes regions which partially extend into and coincide with said source and partially extend into and coincide with said drain, said silicon-germanium layer being in direct contact with said dielectric film and contacting said source and said drain,

7. The transistor according to claim 6, wherein:

said silicon-germanium layer comprises a silicon layer doped with germanium.

8. A transistor according to claim 6, which further comprises:

first and second conductive layers arranged on the substrate body surface to be in contact with said source and said drain, said silicon-germanium layer also being in contact with said first and second conductive layers.

9. The transistor according to claim 6, wherein:

end portions of said silicon germanium layer terminate inside said source and said drain.

10. A bipolar heterostructure transistor, which comprises:

a substrate body made from silicon and having a surface;

a semiconductor collector layer of a first conductivity type in said substrate body;

a semiconductor base region of a second conductivity type provided in the surface of said substrate body;

a base layer below the surface of said substrate body, comprising a silicon-germanium layer having a lateral extent confined to between opposing portions of said base region, said lateral extent including regions partially extending into, coinciding with and ending in said semiconductive base region; and

a semiconductive emitter layer of the first conductivity type which is adjacent to said base layer and disposed in the surface of said substrate body.

11. The transistor according to claim 10, wherein:

said silicon-germanium layer comprises a silicon layer doped with germanium.

12. The transistor according to claim 11, wherein:

said silicon-germanium layer is located below the surface of the substrate body.