Fabrication of complementary n-channel and p-channel circuits (ICs) useful in the manufacture of dynamic random access memories (drams)
First Claim
1. An integrated circuit having complementary n-channel and p-channel devices therein and fabricated by the process of:
- a) defining PMOS and NMOS regions, and forming multi-level layers of conductive and non-conductive transistor gate materials extending across a memory array section and an adjacent peripheral array section of a semiconductor substrate being processed to form a semiconductor device;
b) photo-defining n-channel transistor gates within said memory array section and within NMOS regions in said peripheral array section, while leaving in place said gate electrode layers over the future transistor regions within PMOS regions in said peripheral array section;
c) implanting n-type dopant ions into regions of said memory array section adjacent to said n-channel transistor gates for bit or digit lines for said n-channel transistors and into said NMOS regions in said peripheral array section;
d) depositing and etching dielectric spacers simultaneously into said memory array section into said NMOS regions in said peripheral array section, thereby forming identical spacers on both said memory array section into said NMOS regions in said peripheral array section;
e) implanting source/drain regions into said memory array section into said NMOS regions in said peripheral array section;
f) depositing dielectric and forming digit line contacts;
g) depositing and photoetching digit lines;
h) defining p-channel transistors;
i) forming dielectric spacers simultaneously to digit lines and PMOS transistors, thereby forming identical spacers on both said digit lines and said PMOS transistors;
j) forming stacked capacitor structures on top of said bit or digit lines for said n-channel transistors, wherein conducting transistor gate material forming the word lines in the array and NMOS and PMOS transistors in the periphery have identical film structures;
k) photo-defining p-channel transistor gates within said peripheral array section of said semiconductor substrate, while leaving said memory array section thereof masked against ion implantation; and
l) subsequent to the step of forming dielectric spacers simultaneously to digit lines and PMOS transistors, implanting p-type of n-type dopant ions into regions of said peripheral array section adjacent to either p-channel or n-channel transistor gates therein, respectively, to form bit or digit lines within said peripheral array section, whereby high performance and high frequency p-n junction devices are formed while being exposed to a minimum of temperature cycling and ion-implantation masking steps.
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Abstract
A process for fabricating n-channel and p-channel metal-oxide-semiconductor devices in the manufacture of very large scale integrated circuits, such as high density dynamic random access memories (DRAMs). n-channel and p-channel gate layers of selected conductive and non-conductive materials are initially formed on the surface of a semiconductor substrate, and the n-channel gate layers in a memory array and periphery section of the substrate are initially photodefined, leaving the p-channel gate layers in place over an area of the substrate where future p-channel transistors and P+ active area will be formed. A series of ion implantation steps are then carried out to form the n-channel transistors, therefor using no masking steps, since the in-place gate layers on the p-channel peripheral section serves as an ion implantation mask over this section and thus prevents n-type ions from entering the p-type transistor areas of the peripheral section. Then, the completed n-channel transistors memory section is appropriately masked prior to photo-defining the transistor gate electrodes for either p or n-type transistors in the peripheral section of the substrate. Using this process, not only are the total number of necessary ion implantation masking steps held to an absolute minimum, but the p-channel peripheral section circuits such as sense amplifiers, decoders and drivers, logic circuits, and the like are exposed to a minimum of temperature cycling, thereby enhancing device reliability and improving the high frequency performance of the devices thus produced.
140 Citations
17 Claims
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1. An integrated circuit having complementary n-channel and p-channel devices therein and fabricated by the process of:
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a) defining PMOS and NMOS regions, and forming multi-level layers of conductive and non-conductive transistor gate materials extending across a memory array section and an adjacent peripheral array section of a semiconductor substrate being processed to form a semiconductor device; b) photo-defining n-channel transistor gates within said memory array section and within NMOS regions in said peripheral array section, while leaving in place said gate electrode layers over the future transistor regions within PMOS regions in said peripheral array section; c) implanting n-type dopant ions into regions of said memory array section adjacent to said n-channel transistor gates for bit or digit lines for said n-channel transistors and into said NMOS regions in said peripheral array section; d) depositing and etching dielectric spacers simultaneously into said memory array section into said NMOS regions in said peripheral array section, thereby forming identical spacers on both said memory array section into said NMOS regions in said peripheral array section; e) implanting source/drain regions into said memory array section into said NMOS regions in said peripheral array section; f) depositing dielectric and forming digit line contacts; g) depositing and photoetching digit lines; h) defining p-channel transistors; i) forming dielectric spacers simultaneously to digit lines and PMOS transistors, thereby forming identical spacers on both said digit lines and said PMOS transistors; j) forming stacked capacitor structures on top of said bit or digit lines for said n-channel transistors, wherein conducting transistor gate material forming the word lines in the array and NMOS and PMOS transistors in the periphery have identical film structures; k) photo-defining p-channel transistor gates within said peripheral array section of said semiconductor substrate, while leaving said memory array section thereof masked against ion implantation; and l) subsequent to the step of forming dielectric spacers simultaneously to digit lines and PMOS transistors, implanting p-type of n-type dopant ions into regions of said peripheral array section adjacent to either p-channel or n-channel transistor gates therein, respectively, to form bit or digit lines within said peripheral array section, whereby high performance and high frequency p-n junction devices are formed while being exposed to a minimum of temperature cycling and ion-implantation masking steps. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An integrated circuit having complementary n-channel and p-channel devices therein and fabricated by the process of:
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a) defining PMOS and NMOS regions, and forming multi-level layers of conductive and non-conductive transistor gate materials extending across a memory array section and an adjacent peripheral array section of a semiconductor substrate being processed to form a semiconductor device; b) photo-defining n-channel transistor gates within said memory array section and within NMOS regions in said peripheral array section, while leaving in place said gate electrode layers over future transistor regions within PMOS regions in said peripheral array section; c) implanting n-type dopant ions into regions of said memory array section adjacent to said n-channel transistor gates for bit or digit lines for said n-channel transistors and into said NMOS regions in said peripheral array section; d) depositing and etching dielectric spacers simultaneously into digit lines of said memory array section into said NMOS regions in said peripheral array section, thereby forming identical spacers on both said memory array section into said NMOS regions in said peripheral array section;
p1 e) implanting source/drain regions into said memory array section into said NMOS regions in said peripheral array section;f) depositing a dielectric layer; g) etching through the deposited dielectric layer in order to form bit contact openings; h) depositing a further conductive layer; i) defining p-channel transistors; j) simultaneously forming spacers for both digit lines and PMOS transistors, thereby forming identical spacers on both said digit lines and said PMOS transistors, wherein said dielectric spacers for bit lines isolate digit line sidewalls from subsequent storage capacitor plates; k) forming a capacitor structures in said memory array, wherein conducting transistor gate material forming the word liens in the array and NMOS and PMOS transistors in the periphery have identical film structures; l) photo-defining p-channel transistor gates within said peripheral array section of said semiconductor substrate, while leaving said memory array section thereof masked against ion implantation; and m) subsequent to the step of forming dielectric spacers simultaneously to digit lines and PMOS transistors, implanting dopant ions into regions of said peripheral array section adjacent to transistor gates therein. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A DRAM integrated circuit having complementary n-channel and p-channel devices therein and fabricated by the process of:
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a) patterning NMOS and word line transistors; b) subsequent to patterning said NMOS and word line transistors, forming identical dielectric spacers for bit lines and NMOS transistors source/drain areas, and future isolation of wordlines and bitlines, thereby forming identical spacers on both said memory array section into said NMOS regions in said peripheral array section; c) digit line deposition and patterning; d) subsequent to said forming of said dielectric spacers and subsequent to said digit line deposition, patterning p channel semiconductor material; e) simultaneously forming spacers for both digit lines and p channel transistors, thereby forming identical spacers on both said digit lines and said PMOS transistors, wherein said dielectric spacers for bit lines isolate digit line sidewalls from subsequent storage capacitor plates; and f) depositing storage capacitor plates, wherein conducting transistor gate material forming the word lines in the array and NMOS and PMOS transistors in the periphery have identical film structures. - View Dependent Claims (14, 15, 16, 17)
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Specification