Fabrication of complementary n-channel and p-channel circuits (ICs) useful in the manufacture of dynamic random access memories (drams)

• US 5,272,367 A
• Filed: 12/07/1992
• Issued: 12/21/1993
• Est. Priority Date: 05/02/1988
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Dennison, Charles H., Lowrey, Tyler A.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LIMANEK, ROBERT P
• Application Number:
  US07/988,376
• Time in Patent Office: 379 Days
• Field of Search: 357/23.6, 257/900, 257/306, 257/369, 257/413
• US Class Current: 257/306
• CPC Class Codes: H01L 21/76218 introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A process for fabricating n-channel and p-channel metal-oxide-semiconductor devices in the manufacture of very large scale integrated circuits, such as high density dynamic random access memories (DRAMs). n-channel and p-channel gate layers of selected conductive and non-conductive materials are initially formed on the surface of a semiconductor substrate, and the n-channel gate layers in a memory array and periphery section of the substrate are initially photodefined, leaving the p-channel gate layers in place over an area of the substrate where future p-channel transistors and P+ active area will be formed. A series of ion implantation steps are then carried out to form the n-channel transistors, therefor using no masking steps, since the in-place gate layers on the p-channel peripheral section serves as an ion implantation mask over this section and thus prevents n-type ions from entering the p-type transistor areas of the peripheral section. Then, the completed n-channel transistors memory section is appropriately masked prior to photo-defining the transistor gate electrodes for either p or n-type transistors in the peripheral section of the substrate. Using this process, not only are the total number of necessary ion implantation masking steps held to an absolute minimum, but the p-channel peripheral section circuits such as sense amplifiers, decoders and drivers, logic circuits, and the like are exposed to a minimum of temperature cycling, thereby enhancing device reliability and improving the high frequency performance of the devices thus produced.

Claims

1. An integrated circuit having complementary n-channel and p-channel devices therein and fabricated by the process of:

a) defining PMOS and NMOS regions, and forming multi-level layers of conductive and non-conductive transistor gate materials extending across a memory array section and an adjacent peripheral array section of a semiconductor substrate being processed to form a semiconductor device;

b) photo-defining n-channel transistor gates within said memory array section and within NMOS regions in said peripheral array section, while leaving in place said gate electrode layers over the future transistor regions within PMOS regions in said peripheral array section;

c) implanting n-type dopant ions into regions of said memory array section adjacent to said n-channel transistor gates for bit or digit lines for said n-channel transistors and into said NMOS regions in said peripheral array section;

d) depositing and etching dielectric spacers simultaneously into said memory array section into said NMOS regions in said peripheral array section, thereby forming identical spacers on both said memory array section into said NMOS regions in said peripheral array section;

e) implanting source/drain regions into said memory array section into said NMOS regions in said peripheral array section;

f) depositing dielectric and forming digit line contacts;

g) depositing and photoetching digit lines;

h) defining p-channel transistors;

i) forming dielectric spacers simultaneously to digit lines and PMOS transistors, thereby forming identical spacers on both said digit lines and said PMOS transistors;

j) forming stacked capacitor structures on top of said bit or digit lines for said n-channel transistors, wherein conducting transistor gate material forming the word lines in the array and NMOS and PMOS transistors in the periphery have identical film structures;

k) photo-defining p-channel transistor gates within said peripheral array section of said semiconductor substrate, while leaving said memory array section thereof masked against ion implantation; and

l) subsequent to the step of forming dielectric spacers simultaneously to digit lines and PMOS transistors, implanting p-type of n-type dopant ions into regions of said peripheral array section adjacent to either p-channel or n-channel transistor gates therein, respectively, to form bit or digit lines within said peripheral array section, whereby high performance and high frequency p-n junction devices are formed while being exposed to a minimum of temperature cycling and ion-implantation masking steps.

2. An integrated circuit as defined in claim 1, further including:

insulating spacers formed on sidewalls of said n-channel and p-channel gates to improve the short channel characteristics of p-channel and n-channel transistors and bit lines, and further forming insulating spacers between adjacent stacked capacitor structures and located on top of said n-channel transistor gates.

3. An integrated circuit as defined in claim 1, further including:

said n-channel and p-channel gates being constructed by forming a first level of polycrystalline silicon followed by a second layer of tungsten silicide followed by a third layer of silicon dioxide.

4. An integrated circuit as defined in claim 1, further including:

said stacked capacitor structures being constructed by forming a first level of polycrystalline silicon followed by a second level of tungsten silicide followed by a third level of silicon dioxide followed by an overlying capacitor plate layer.

5. An integrated circuit as defined in claim 4, further including:

said n-channel and p-channel gates being constructed by forming a first level of polycrystalline silicon followed by a second layer of tungsten silicide followed by a third layer of silicon dioxide.

6. An integrated circuit as defined in claim 1, further including:

said n-channel and p-channel gates and said stacked capacitor structures are constructed by forming a first layer of polycrystalline silicon adjacent to the surface of said semiconductor substrate followed by a second layer of tungsten silicide formed atop said polycrystalline silicon layer, followed by a third layer of silicon dioxide formed atop said tungsten silicide layer.

7. An integrated circuit having complementary n-channel and p-channel devices therein and fabricated by the process of:

a) defining PMOS and NMOS regions, and forming multi-level layers of conductive and non-conductive transistor gate materials extending across a memory array section and an adjacent peripheral array section of a semiconductor substrate being processed to form a semiconductor device;

b) photo-defining n-channel transistor gates within said memory array section and within NMOS regions in said peripheral array section, while leaving in place said gate electrode layers over future transistor regions within PMOS regions in said peripheral array section;

c) implanting n-type dopant ions into regions of said memory array section adjacent to said n-channel transistor gates for bit or digit lines for said n-channel transistors and into said NMOS regions in said peripheral array section;

d) depositing and etching dielectric spacers simultaneously into digit lines of said memory array section into said NMOS regions in said peripheral array section, thereby forming identical spacers on both said memory array section into said NMOS regions in said peripheral array section;

p1 e) implanting source/drain regions into said memory array section into said NMOS regions in said peripheral array section;

f) depositing a dielectric layer;

g) etching through the deposited dielectric layer in order to form bit contact openings;

h) depositing a further conductive layer;

i) defining p-channel transistors;

j) simultaneously forming spacers for both digit lines and PMOS transistors, thereby forming identical spacers on both said digit lines and said PMOS transistors, wherein said dielectric spacers for bit lines isolate digit line sidewalls from subsequent storage capacitor plates;

k) forming a capacitor structures in said memory array, wherein conducting transistor gate material forming the word liens in the array and NMOS and PMOS transistors in the periphery have identical film structures;

l) photo-defining p-channel transistor gates within said peripheral array section of said semiconductor substrate, while leaving said memory array section thereof masked against ion implantation; and

m) subsequent to the step of forming dielectric spacers simultaneously to digit lines and PMOS transistors, implanting dopant ions into regions of said peripheral array section adjacent to transistor gates therein.

8. An integrated circuit as defined in claim 7, further including:

insulating spacers formed on sidewalls of said n-channel and p-channel gates to improve the short channel characteristics of p-channel and n-channel transistors and bit liens, and further forming insulating spacers between adjacent stacked capacitor structures and located on top of said n-channel transistor gates.

9. An integrated circuit as defined in claim 7, further including:

said n-channel and p-channel gates being constructed by forming a first level of polycrystalline silicon followed by a second layer of tungsten silicide followed by a third layer of silicon dioxide.

10. An integrated circuit as defined in claim 7, further including:

said stacked capacitor structures being constructed by forming a first level of polycrystalline silicon followed by a second level of tungsten silicide followed by a third level of silicon dioxide followed by an overlying capacitor plate layer.

11. An integrated circuit as defined in claim 7, further including:

said n-channel and p-channel transistor gates being constructed by forming a first level of polycrystalline silicon followed by a second layer of tungsten silicide followed by a third layer of silicon dioxide.

12. An integrated circuit as defined in claim 11, further including:

said n-channel and p-channel gates and said stacked capacitor structures are constructed by forming a first layer of polycrystalline silicon adjacent to the surface of said semiconductor substrate followed by a second layer of tungsten silicide formed atop said polycrystalline silicon layer, followed by a third layer of silicon dioxide formed atop said tungsten silicide layer.

13. A DRAM integrated circuit having complementary n-channel and p-channel devices therein and fabricated by the process of:

a) patterning NMOS and word line transistors;

b) subsequent to patterning said NMOS and word line transistors, forming identical dielectric spacers for bit lines and NMOS transistors source/drain areas, and future isolation of wordlines and bitlines, thereby forming identical spacers on both said memory array section into said NMOS regions in said peripheral array section;

c) digit line deposition and patterning;

d) subsequent to said forming of said dielectric spacers and subsequent to said digit line deposition, patterning p channel semiconductor material;

e) simultaneously forming spacers for both digit lines and p channel transistors, thereby forming identical spacers on both said digit lines and said PMOS transistors, wherein said dielectric spacers for bit lines isolate digit line sidewalls from subsequent storage capacitor plates; and

f) depositing storage capacitor plates, wherein conducting transistor gate material forming the word lines in the array and NMOS and PMOS transistors in the periphery have identical film structures.

14. A DRAM integrated circuit as defined in claim 13, further including:

insulating spacers formed on sidewalls of said n-channel and p-channel gates to improve the short channel characteristics of p-channel and n-channel transistors and bit lines, and further forming insulating spacers between adjacent stacked capacitor structures and located on top of said n-channel transistor gates.

15. A DRAM integrated circuit as defined in claim 13, further including:

n-channel and p-channel gates constructed by forming a first level of polycrystalline silicon followed by a second layer of tungsten silicide followed by a third layer of silicon dioxide.

16. A DRAM integrated circuit as defined in claim 13, further including:

stacked capacitor structures, said stacked capacitor structures being constructed by forming a first level of polycrystalline silicon followed by a second level of tungsten silicide followed by a third level of silicon dioxide followed by an overlying capacitor plate layer.

17. A DRAM integrated circuit as defined in claim 16, further including:

n-channel and p-channel gates and said stacked capacitor structures are constructed by forming a first layer of polycrystalline silicon adjacent to the surface of said semiconductor substrate followed by a second layer of tungsten silicide formed atop said polycrystalline silicon layer, followed by a third layer of silicon dioxide formed atop said tungsten silicide layer.