Complementary low power non-volatile reconfigurable EEcell

• US 5,272,368 A
• Filed: 05/10/1991
• Issued: 12/21/1993
• Est. Priority Date: 05/10/1991
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Cliff, Richard G., Turner, John E.
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US07/698,084
• Time in Patent Office: 956 Days
• Field of Search: 365/185, 365/189.05, 365/189.08, 365/189.09, 257/315
• US Class Current: 365/185.1
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/045 Floating gate memory cells with both P and N channel memory transistors, usually sharing a common floating gate
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile CMOS electrically erasable programmable memory cell for configuring a PLD is disclosed. A CMOS inverter is formed by fabricating an n-channel MOSFET and a p-channel MOSFET with merged floating gate regions. A tunnel capacitor allows charge to be supplied to or removed from the floating gate. The floating gate provides non-volatile charge storage. The CMOS inverter senses the presence or absence of charge on the floating gate and provides an amplified inverted output. The CMOS inverter consumes very low power and provides rail-to-rail output voltage swings.

Claims

1. In a programmable logic device, a configuration cell comprising:

a common floating gate;

an output node;

a write node;

a control gate;

a p-channel MOS device with a source coupled to a first voltage, a drain coupled to said output node, and a gate coupled to said common floating gate;

an n-channel MOS device with a drain coupled to said output node and to said drain of said p-channel MOS device, a source coupled to a second voltage, a gate coupled to said common floating gate, said MOS devices being coupled together such that in a steady state, only one of said MOS devices conducts;

a tunnel capacitor, for providing charge to and removing charge from said common floating gate, having its first terminal coupled to said common floating gate and its other terminal coupled to said write node; and

a capacitor having its first terminal coupled to said common floating gate and its other terminal coupled to said control gate.

2. The configuration cell of claim 1 wherein one of said first and second voltage sources is set to a voltage representing a logical low state and the other voltage source is set to a voltage representing a logical high state, such that the voltage at said output node varies unambiguously between a first one of said logical low state and said logical high state and a second one of said logical low state and said logical high state as said common floating gate varies between a charged state and a discharged state.

3. A configuration cell comprising:

a common floating gate;

an output node;

a write node;

a control gate;

a capacitor for storing charge, having its first terminal coupled to said control gate and its second terminal coupled to said common floating gate;

a tunnel capacitor for charging and discharging said common floating gate, having its first terminal coupled to said write node and its second terminal coupled to said common floating gate;

an n-channel MOS device having its source coupled to a first voltage node, its substrate coupled to said source, and its drain coupled to said output node and said common floating gate disposed over the channel between the source and the drain; and

a p-channel MOS device having its source coupled to a second voltage node, its substrate coupled to said source, its drain coupled to said output node and to said drain of said n-channel MOS device, and said common floating gate disposed over the channel between the source and the drain, said MOS devices being coupled such that in a steady state, only one of said MOS devices conducts.

4. The device of claim 3 wherein a first pass transistor having a write select signal coupled to its gate couples said write node to an external write line, and a second pass transistor having a verify signal coupled to its gate couples said output node to an external verify line.

5. The configuration cell of claim 3 wherein one of said first and second voltage nodes is set to a voltage representing a logical low state and the other voltage node is set to a voltage representing a logical high state, such that the voltage at said output node varies unambiguously between a first one of said logical low state and said logical high state and a second one of said logical low state and said logical high state as said common floating gate varies between a charged state and a discharged state.

6. In a programmable logic device, a configuration cell comprising:

a control gate;

a storage node;

a write node;

an output node;

a p-channel MOSFET with its source connected to a first voltage, its drain connected to said output node, and its gate connected to said storage node;

an n-channel MOSFET with its drain connected to said output node and to said drain of said p-channel MOSFET, its source connected to a second voltage and its gate connected to said storage node, said MOSFETS being coupled such that in a steady state, only one of said MOSFETS conducts;

a tunnel capacitor, for providing and removing charge from said storage node, having its first terminal connected to said storage node and its other terminal connected to said write node; and

a capacitor for storing charge, having its first terminal connected to said storage node and its other terminal connected to said control gate.

7. The configuration cell of claim 6 wherein one of said first and second voltages is set to a voltage representing a logical low state and the other voltage is set to a voltage representing a logical high state, such that the voltage at said output node varies unambiguously between a first one of said logical low state and said logical high state and a second one of said logical low state and said logical high state as said storage node varies between a charged state and a discharged state.

8. A configuration cell comprising:

a storage node;

an output node;

a control gate;

a write node;

a write select node;

a write line;

a verify line;

a verify select node;

a CMOS invertor having its input coupled to said storage node and its output coupled to said output node, said invertor being configured such that substantially no power is consumed during normal operation;

a capacitor having a first terminal coupled to said storage node and a second terminal coupled to said control gate;

a tunnel capacitor having a first terminal coupled to said storage node and a second terminal coupled to said write node;

a first pass transistor having a drain coupled to said write node, a gate coupled to said write select node and a source coupled to said write line; and

a second pass transistor having a source coupled to said verify line, a gate coupled to said verify select node, and a drain coupled to said output node.

9. The configuration cell of claim 8 wherein said invertor is further coupled to first and second voltage nodes where one of said voltage nodes is set to a voltage representing a logical low state and the other voltage node is set to a voltage representing a logical high state, such that the voltage at said output node varies unambiguously between a first one of said logical low state and said logical high state and a second one of said logical low state and said logical high state as said storage node varies between a charged state and a discharged state.

10. A configuration cell comprising:

floating gate means for storing charge;

programming means including a tunnel capacitor for charging and discharging the floating gate; and

means for sensing the charge on the floating gate and providing an amplified output representative of the charge and consuming an amount of power approaching zero.

11. The configuration cell of claim 10 wherein the programming means includes a pass transistor gated by a write select signal for coupling inputs to said tunnel capacitor from a write node.

12. The configuration cell of claim 11 wherein the means for sensing the charge on the floating gate and providing an amplified output representative of the charge comprises a CMOS invertor.

13. The configuration cell of claim 12 wherein the output means includes a pass transistor gated by a verify select signal for coupling the output of the CMOS invertor to a verify node.

14. The configuration cell of claim 13 including means for verifying a voltage margin.

15. The configuration cell of claim 10 wherein said means for sensing is coupled to first and second voltage supply means where one of said voltage supply means is set to a voltage representing a logical low state and the other voltage supply means is set to a voltage representing a logical high state, such that said amplified output representative of the charge varies unambiguously between a first one of said logical low state and said logical high state and a second one of said logical low state and said logical high state as said floating gate varies between a charged state and a discharged state.