Electrostatic discharge protection structure

• US 5,272,371 A
• Filed: 11/19/1991
• Issued: 12/21/1993
• Est. Priority Date: 11/19/1991
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Zamanian, Mehdi, Bishop, William A., Chan, Tsiu C.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/794,488
• Time in Patent Office: 763 Days
• Field of Search: 357/23.13, 357/35, 357/40, 357/41, 257/361, 257/362
• US Class Current: 257/362
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

An ESD protection circuit and structure for implementation within an integrated circuit is disclosed. The protection circuit includes a diode, serving as a triggering device, and a lateral bipolar transistor. The triggering voltage of said diode is selected by an implant underlying a first field oxide structure adjacent a first diffused region to which the external terminal is connected. The lateral bipolar transistor uses the first diffused region to which the external terminal is connected as the collector region, a second diffused region opposite the first field oxide structure from said first diffused region as the emitter, and the substrate, or epitaxial layer, as the base. A second field oxide structure encircles the emitter region and has a distance thereacross which is selected in order to provide sufficient base resistance that, upon junction breakdown of the diode, the base-emitter junction of the lateral transistor is forward biased and the transistor turned on.

Claims

1. An ESD protection circuit for an integrated circuit, comprising:

first and second terminals, said first terminal for communicating signals externally from said integrated circuit;

a first doped region at a semiconducting surface of a body, doped to a first conductivity type and connected to said fist terminal, said semiconducting surface being doped to a second conductivity type;

a first insulating structure at said surface, said first insulating structure defining an outer edge of said first doped region, and overlying a portion of said semiconducting surface of said second conductivity type;

a second doped region at said surface and substantially surrounding said first insulating structure, said second doped region doped to said first conductivity type and coupled to said second terminal;

a second insulating structure at said surface and substantially surrounding said second doped region, a substantial portion of the length of said second insulating structure located around a perimeter of said second doped region; and

a third doped region at said surface and substantially surrounding said second insulating structure, said third doped region doped to said second conductivity type and coupled to said second terminal;

wherein the distance across said second insulating structure from said second doped region to said third doped region is substantially uniform around the perimeter of said second doped region.

2. The circuit of claim 1, wherein said first conductivity type is p-type and said second conductivity type is n-type;

and further comprising;

a fourth doped region, underlying said first insulating structure, said fourth doped region being n-type and more heavily doped than said semiconducting surface.

3. The circuit of claim 1, further comprising:

a first well region of said first conductivity type and underlying a portion of said first doped region.

4. The circuit of claim 3, wherein said first terminal is connected to said first doped region by way of a metal contact thereto;

and wherein said first well region underlies the location of said metal contact.

5. The circuit of claim 4, wherein said first well region does not underlie a portion of said first doped region adjacent said first insulating structure.

6. The circuit of claim 4, further comprising:

a second well region of said first conductivity type and underlying a portion of said second doped region;

wherein said second terminal is connected to said second doped region by way of a metal contact thereto;

and wherein said second well region underlies the location of said metal contact to said second doped region.

7. The circuit of claim 1, wherein said first terminal is an input terminal.

8. The circuit of claim 7, further comprising:

an input buffer circuit; and

a resistor connected between said first doped region and said input buffer circuit.

9. The circuit of claim 1, wherein said first terminal is an output terminal.

10. An ESD protection circuit for an integrated circuit, comprising:

first and second terminals, said first terminal for communicating signals externally from said integrated circuit;

a first doped region at a semiconducting surface of a body, doped to a first conductivity type and connected to said first terminal, said semiconducting surface being doped to a second conductivity type;

a first insulating structure at said surface, said first insulating structure defining an outer edge of said first doped region, and overlying a portion of said semiconducting surface of said second conductivity type;

a second doped region at said surface and substantially surrounding said first insulating structure, said second doped region doped to said first conductivity type and coupled to said second terminal;

a second insulating structure at said surface and substantially surrounding said second doped region, a substantial portion of the length of said second insulating structure located around a perimeter of said second doped region; and

a third doped region at said surface and substantially surrounding said second insulating structure, said third doped region doped said second conductivity type and coupled to said second terminal;

wherein the distance across said second insulating structure from said second doped region to said third doped region is substantially uniform around the perimeter of said second doped region;

and wherein the distance across said second insulating structure is greater than the distance across said first insulating structure from said first doped region to said second doped region.

11. In an integrated circuit having a first terminal and a power supply terminal, said integrated circuit formed at a semiconducting surface of a body, said surface having a first conductivity type, a protection circuit against electrostatic discharge comprising:

a diode, having a first side connected to said first terminal and a second side connected to said semiconducting surface;

a lateral bipolar transistor, comprising;

a collector region of a second conductivity type formed at said surface, and connected to said first side of said diode;

an emitter region of said second conductivity type formed at said surface, and coupled to said power supply terminal, and separated from said collector region by a first insulating structure at said surface therebetween, said emitter region and said first insulating structure substantially surrounding a perimeter of said collector region; and

a base contact region of said first conductivity type formed at said surface, and coupled to said power supply terminal, said base contact region separated from said emitter region by a second insulating structure at said surface therebetween, said base contact region and said second insulating structure substantially surrounding a perimeter of said emitter region; and

a resistor, defined by a portion of said semiconducting surface under said second insulating structure between said emitter region and said base contact region, the distance across said second insulating structure between said emitter region and said base contact region being substantially uniform over most of its length to define a resistance value sufficient to forward bias a junction between said surface and said emitter region responsive to said diode being in a junction breakdown condition.

12. The circuit of claim 11, wherein said first conductivity type is n-type and said second conductivity type is p-type.

13. The circuit of claim 12, further comprising:

an n-type doped region underlying said first insulating structure, said n-type doped region being more heavily doped than said semiconducting surface.

14. The circuit of claim 11, further comprising:

a doped region of said first conductivity type underlying said first insulating structure, said doped region being more heavily doped than said semiconducting surface.

15. The circuit of claim 11, further comprising:

functional circuitry coupled to said first terminal.

16. The circuit of claim 15, further comprising:

an input buffer coupled between said first terminal and said functional circuitry.

17. The circuit of claim 11, wherein said first terminal is coupled to said first side of said diode by a metal contact to said collector region;

and further comprising a well, of said second conductivity type, underlying the location at which said metal contact is made to said collector region.

18. The circuit of claim 11, wherein said first side of said diode consists of said collector region.

19. The circuit of claim 18, wherein a portion of said collector region located adjacent said first insulating structure directly forms thereat a metallurgical p-n junction with said semiconducting surface.

20. In an integrated circuit having a first terminal and a power supply terminal, said integrated circuit formed at a semiconducting surface of a body, said surface having a first conductivity type, a protection circuit against electrostatic discharge comprising:

a diode, having a first side connected to said first terminal and a second side connected to said semiconducting surface;

a lateral bipolar transistor, comprising;

a collector region of a second conductivity type formed at said surface, and connected to said first side of said diode;

an emitter region of said second conductivity type formed at said surface, and coupled to said power supply terminal, and separated from said collector region by a first insulating structure at said surface therebetween, said emitter region and said first insulating structure substantially surrounding a perimeter of said collector region; and

a base contact region of said first conductivity type formed at said surface, and coupled to said power supply terminal, said base contact region separated from said emitter region by a second insulating structure at said surface therebetween, said base contact region and said second insulating structure substantially surrounding a perimeter of said emitter region; and

a resistor, defined by a portion of said semiconducting surface under said second insulating structure between said emitter region and said base contact region, the distance across said second insulating structure between said emitter region and said base contact region being substantially uniform over most of its length to define a resistance value sufficient to forward bias a junction between said surface and said emitter region responsive to said diode being in a junction breakdown condition;

and wherein the distance across said second insulating structure is significantly greater than the distance across the first insulating structure.