Digital controlled inverter and method
First Claim
1. A digital controlled inverter comprising:
- signal;
latching means for controlling the passage of said clock timing signal to an output stage;
power means located within said output stage for providing a low distortion alternating current signal, said power means controlled by said latching means; and
control loop means for sensing and converting said alternating current signal to a command signal,wherein said command signal controls the state of said latching means, said latching means being reset at the rate of said clock timing signal and updated with said command signal to provide pulse-to-pulse regulation of said alternating current signal, said inverter comprising a transient response to variations in load proportional to said clock timing signal.
1 Assignment
0 Petitions
Accused Products
Abstract
A digital controlled inverter (100) for inverting an input signal to an alternating current signal having a clock generator (104) for generating a high frequency clock timing signal and a latch (106) for controlling the passage of the clock timing signal to a power stage (102). The power stage (102), which provides a low distortion alternating current signal, is controlled by the latch (106). A control loop (108) is provided for sensing and converting the alternating current signal to a command signal. The command signal controls the state of the latch (106). The latch (106) is reset at the rate of the clock timing signal and updated with the command signal to provide pulse-to-pulse regulation of the alternating current signal. The inverter (100) comprises a transient response to variations in load proportional to the clock timing signal. In a preferred embodiment, the latch (106) functions as a switch for controlling the power output stage (102). The control loop (108) serves to provide the command signal to operate the latch (106). The alternating current signal is rectified and converted to a digital word and then compared to a reference digital word in a digital comparator (138) to provide the command signal to the latch (106).
-
Citations
20 Claims
-
1. A digital controlled inverter comprising:
- signal;
latching means for controlling the passage of said clock timing signal to an output stage; power means located within said output stage for providing a low distortion alternating current signal, said power means controlled by said latching means; and control loop means for sensing and converting said alternating current signal to a command signal, wherein said command signal controls the state of said latching means, said latching means being reset at the rate of said clock timing signal and updated with said command signal to provide pulse-to-pulse regulation of said alternating current signal, said inverter comprising a transient response to variations in load proportional to said clock timing signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
- signal;
-
16. A digital controlled inverter comprising:
-
a clock generator for generating a high frequency clock timing signal; a latch for controlling the passage of said clock timing signal to an output stage; power means located within said output stage for providing a low distortion alternating current signal, said power means controlled by said latch; and control loop means for sensing and converting said alternating current signal to a command signal, wherein said command signal controls the state of said latch, said latch being reset at the rate of said clock timing signal and updated with said command signal to provide pulse-to-pulse regulation of said alternating current signal, said inverter comprising a transient response to variations in load proportional to said clock timing signal.
-
-
17. A method for providing digital controlled inversion of an input signal to an alternating current signal, said method comprising the steps of:
-
generating a high frequency clock timing signal; controlling the passage of said clock timing signal to an output stage; providing a low distortion alternating current signal from said output stage controlled by a latch; sensing and converting said alternating current signal to a command signal; latching said command signal and controlling the state of said latch with said command signal; resetting said latch at the rate of said clock timing signal; updating said latch with said command signal to provide pulse-to-pulse regulation of said alternating current signal; and providing a transient response to variations in load proportional to said clock timing signal. - View Dependent Claims (18, 19, 20)
-
Specification