Method and structure for programming floating gate memory cells
First Claim
1. A method for operating an Electrically Erasable Programmable Read Only Memory (EEPROM) having a plurality of memory cells, each of said memory cells comprising a source, a drain, a channel region having a first and a second portion lying between said source and drain with said second portion adjacent said source and serving as the channel of a select transistor, a floating gate above said first portion of said channel region, and a control gate having a first portion above said floating gate and a second portion above said second portion of said channel region, comprising the steps of:
- erasing a plurality of said memory cells; and
performing a recovery step by applying a potential voltage difference between said source and drain of sufficient magnitude for hot electron programming to occur, and a voltage approximately equal to the threshold voltage of said second portion of said channel region of said memory cells to said control gate, in which the floating gate voltages of said overerased cells are reduced while substantially not affecting the floating gate voltages of memory cells which are not overerased, whereby those of said plurality of said memory cells which have been overerased during said step of erasing are made to be less overerased in preparation for a subsequent programming step.
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Accused Products
Abstract
A novel method and structure are taught for narrowing the distribution of charge on the floating gates after electrical erasure of a population of cells. This allows faster programming following erasure. An additional recovery step is performed after erasure and prior to programming. The recovery step serves to adjust the state of erasure of the cells such that the distribution of the amount of erasure of each cell in the population of cells is reduced. This is accomplished in order to cause those cells which would have a relatively high floating gate voltage VFG after erasure to be recovered such that their floating gate voltage is made less positive, while having little or no effect on the floating gate voltage of cells which are not overerased. The recovery is performed either as a final step in the erase operation, a separate recovery step independent of the erase or program operations, or as a preliminary step during the programming operation. Recovery can be performed on all memory cells simultaneously, blocks or groups of memory cells in sequence, or individual memory cells in sequence. The recovery step is performed utilizing a low control gate voltage, which voltage is approximately equal to or slightly greater than the threshold voltage of the select transistor, which generates a relatively high floating gate current for over-erased cells, causing them to be significantly less over-erased.
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Citations
26 Claims
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1. A method for operating an Electrically Erasable Programmable Read Only Memory (EEPROM) having a plurality of memory cells, each of said memory cells comprising a source, a drain, a channel region having a first and a second portion lying between said source and drain with said second portion adjacent said source and serving as the channel of a select transistor, a floating gate above said first portion of said channel region, and a control gate having a first portion above said floating gate and a second portion above said second portion of said channel region, comprising the steps of:
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erasing a plurality of said memory cells; and performing a recovery step by applying a potential voltage difference between said source and drain of sufficient magnitude for hot electron programming to occur, and a voltage approximately equal to the threshold voltage of said second portion of said channel region of said memory cells to said control gate, in which the floating gate voltages of said overerased cells are reduced while substantially not affecting the floating gate voltages of memory cells which are not overerased, whereby those of said plurality of said memory cells which have been overerased during said step of erasing are made to be less overerased in preparation for a subsequent programming step. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method for operating an EEPROM comprising a plurality of memory cells which in turn comprise a first plurality of overerased memory cells and a second plurality of non-overerased memory cells, each of said memory cells comprising a source, a drain, a channel region having a first and a second portion lying between said source and drain with said second portion adjacent said source and serving as the channel of a select transistor, a floating gate above said first portion of said channel region, and a control gate having a first portion above said floating gate and a second portion above said second portion of said channel region, comprising the steps of:
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performing a recovery step to cause said first plurality of overerased memory cells to become less overerased by applying a potential voltage difference between said source and drain of sufficient magnitude for hot electron programming to occur, and a voltage approximately equal to the threshold voltage of said second portion of said channel region of said memory cells to said control gate, in which the floating gate voltages of said overerased cells are reduced while substantially not affecting the floating gate voltages of memory cells which are not overerased; and programming said first and second plurality of memory cells. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification