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Method and structure for programming floating gate memory cells

  • US 5,272,669 A
  • Filed: 02/20/1991
  • Issued: 12/21/1993
  • Est. Priority Date: 02/20/1991
  • Status: Expired due to Term
First Claim
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1. A method for operating an Electrically Erasable Programmable Read Only Memory (EEPROM) having a plurality of memory cells, each of said memory cells comprising a source, a drain, a channel region having a first and a second portion lying between said source and drain with said second portion adjacent said source and serving as the channel of a select transistor, a floating gate above said first portion of said channel region, and a control gate having a first portion above said floating gate and a second portion above said second portion of said channel region, comprising the steps of:

  • erasing a plurality of said memory cells; and

    performing a recovery step by applying a potential voltage difference between said source and drain of sufficient magnitude for hot electron programming to occur, and a voltage approximately equal to the threshold voltage of said second portion of said channel region of said memory cells to said control gate, in which the floating gate voltages of said overerased cells are reduced while substantially not affecting the floating gate voltages of memory cells which are not overerased, whereby those of said plurality of said memory cells which have been overerased during said step of erasing are made to be less overerased in preparation for a subsequent programming step.

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