Method of making a solid state electromagnetic radiation detector

• US 5,273,910 A
• Filed: 05/05/1992
• Issued: 12/28/1993
• Est. Priority Date: 08/08/1990
• Status: Expired due to Fees

• Current Assignee: Minnesota Mining and Manufacturing Co (3M Company)
• Original Assignee: Minnesota Mining and Manufacturing Co (3M Company)
• Inventors: Tran, Nang T., Loeding, Neil W., Nins, deceased, David V.
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US07/880,309
• Time in Patent Office: 602 Days
• Field of Search: 437/1, 437/2, 437/3, 437/4, 437/5, 437/48, 437/49, 437/185, 437/195, 250/338, 250/340
• US Class Current: 438/69
• CPC Class Codes: H01L 27/146 Imager structures

Abstract

The present invention provides a large area, high pixel density solid state radiation detector with a real-time and a non-destructive read-out. The solid state detector comprises a plurality of field effect transistors deposited onto a substrate to form an array. A planarization layer is deposited over the array of transistors. An energy sensitive layer is deposited onto the planarization layer. Means is provided for electrically connecting the energy sensitive layer with each transistor of the array. A top electrode layer is deposited onto the energy sensitive layer. The solid state detector also comprises circuitry means for providing electronic read-out from each FET of the array.

Claims

1. A method of making a solid state detector for detecting electromagnetic energy, comprising the steps of:

(a) depositing a plurality of field effect transistors onto a substrate to form an array, wherein each of the field effect transistors has a gate electrode, and wherein a portion of the substrate contiguous to the field effect transistors is an insulating material;

(b) depositing a planarization layer over the array of field effect transistors, wherein the planarization layer is formed from an insulating material, and wherein the planarization layer has a planarized upper surface;

(c) depositing an energy sensitive layer onto the planarization layer, wherein the energy sensitive layer has an additional capacitance;

(d) depositing a plurality of bottom electrodes interposed between the planarization layer and the energy sensitive layer, wherein each bottom electrode is electrically coupled to the gate electrode of a single field effect transistor;

(e) depositing a top electrode layer onto the energy sensitive layer; and

(f) depositing circuitry means for providing electronic read-out from each field effect transistor of the array.

2. The method of claim 1, wherein the field effect transistors are polysilicon-based.

3. The method of claim 1, wherein the field effect transistors are single crystal silicon-based.

4. The method of claim 1, wherein the field effect transistors are hydrogenated amorphous silicon-based.

5. The method of claim 1, wherein the field effect transistors are cadmium selenide-based.

6. The method of claim 1, wherein the energy sensitive layer comprises an x-ray sensitive material.

7. The method of claim 1, wherein the energy sensitive layer comprises a visible light sensitive material.

8. The method of claim 1, wherein the energy sensitive layer comprises an infrared sensitive material.

9. The method of claim 1, wherein the energy sensitive layer comprises an ultraviolet sensitive material.

10. The method of claim 1, wherein the energy sensitive layer comprises a material selected from the group consisting of amorphous selenium;

cadmium telluride;

cadmium selenide;

cadmium sulfide;

mercury cadmium telluride;

selenium-based alloys;

telluride-based alloys;

selenium-tellurium;

hydrogenated amorphous silicon and alloys thereof;

polyvinylidene fluoride ("PVF₂ ");

a blend of PVF₂ and at least one polymer which is miscible with PVF₂ at a temperature above the melting point of PVF₂ ;

vinyl fluoride;

vinyl chloride;

vinylidene chloride;

chlorofluorovinylidene;

trifluoroethylene;

poly-N-vinyl-carbazole;

trinitrofluorenone;

lithium niobate;

lithium tantalate;

Sr_1-x Ba₂ O_x ;

pyrargyrite;

Tl₃ AsSe₃ ;

PbO;

ZnO; and

organic photoconductive materials.

11. The method of claim 1, wherein the energy sensitive layer is a blend of PVF₂ and at least one polymer which is miscible with PVF₂ at a temperature above the melting point of PVF₂.

12. The method of claim 1, wherein the density of the field effect transistors in the array is more than 50×

50 field effect transistors per square centimeter.

13. The method of claim 1, further comprising the step of depositing a phosphor layer onto the top of the solid state detector.

14. The method of claim 13, wherein the phosphor layer comprises a compound selected from the group consisting of Gd₂ O₂ S:

Tb;

BaFBr;

Eu;

Sr₅ SiO₄ ;

SrSO₄ ; and

ZnS;

Cu;

Pb.

15. The method of claim 1, further comprising the step of interposing an insulating layer for additional charge storage between the planarization layer and the energy sensitive layer.