Method of estimating logic cell delay time

• US 5,274,568 A
• Filed: 12/05/1990
• Issued: 12/28/1993
• Est. Priority Date: 12/05/1990
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: NCR Corporation (NCR Voyix Corporation)
• Inventors: Scott, John, Holzer, Richard J. Jr., Ozman, Rhea R., Ouellette, Timothy R., Blinne, Richard D., Laubhan, Richard A.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Ramirez, Ellis B.
• Application Number:
  US07/623,310
• Time in Patent Office: 1,119 Days
• Field of Search: 364/488, 364/489, 364/490, 364/578, 364/569, 395/500, 307/601, 307/605
• US Class Current: 716/108
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method for approximating the delay time of an excitation through a logic cell using the summation of a base delay, which is a function of delay coefficients for the cell and the total output load capacitance of the cell, and a rise/fall time correction, which is determined from the output rise/fall time of the driving cell and the sensitivity of the analyzed cell to rise/fall time. Other corrections/compensating factors include a performance derating factor which accounts for the multiplicative effects of operating voltage, temperature and process.

Claims

1. A method of determinig a delay time for a signal through a logic cell having at least one input pin and at least one output pin, comprising:

(1) providing input data characteristic of the logic cell, said data including cell type, total capacitive load at said at least one input pin, total capacitive load at said at leas one output pin, and slew rate of a simulated signal applied to said at least on input pin, (2) providing a database of predetermined library ell data including base delay computation facts and sensitivity factors for a range of library cell types, (3) determinig from said input data and from said predetermined library cell data at least one edge delay base factor which approximates the delay time of an associated edge of a signal through the logic cell, said associated edge associated with a corresponding edge of said simulated signal, the delay time selected from at least one of a rising edge delay time associated with the rising edge of the signal and a falling edge delay time associated with the falling edge of the signal (4) determining a correction factor based substantially on the slew rate of the corresponding edge of said stimulated signal, and (5) adding said correction factor to said base delay factor to emulate delay time through the cell.

2. The method of claim 1, wherein the rising and falling edge delay correction factors correspond to the rising and falling edges of a signal traversing a non-inverting path, and are, respectively, MAX [0, MCLH*(Trise-Krise)] and MAX [0, MCHL*(Tfall-Kfall)];

and

wherein the MAX function selects the highest one of the values separated by commas and located within the square brackets;

MCLH and MCHL are an input rise time sensitivity factor and an input fall time sensitivity factor, respectively, which measure the effect on the cell of the slew rate of the signal traversing the input pin of the cell;

Trise and Tfall are the rise time and the fall time, respectively, at the input pin of the cell; and

Krise and Kfall are the standard rise time and the standard fall time, respectively, which remove the effects of utilizing the rise and fall times of an ideal simulated signal.

3. The method of claim 2, wherein Trise=(RFC₁ +RFC₂ *CL_IN)*DF_n-1 ;

Tfall=(RFC₃ +RFC₄ *CL_IN)*DF_n-1 ; and

wherein RFC₁ through RFC₄ are coefficients which correspond to the rise and fall times of the signal traversing the input pin of the cell;

CL_IN is the total capacitive load on the input pin of the cell; and

DF_n-1 is the total propagation delay derating factor of a cell which interfaces the cell at the input pin.

4. The method of claim 1, wherein the rising and falling edge delay correction factors which correspond to the rising and falling edges of a signal traversing an inverting path comprise, respectively, MAX [0, MCLH*(Tfall-Krise)] and MAX [0, MCHL*(Trise-Kfall)];

and

wherein the MAX function selects the highest one of the values separated by commas and located within square brackets;

MCLH and MCHL are the input rise time sensitivity factor and the input fall time sensitivity factor, respectively, which measure the effect on the cell of the slew rate of the signal traversing the input pin of the cell;

Trise and Tfall are the rise time and the fall times, respectively, at the input pin of the cell; and

Krise and Kfall are the standard rise time and standard fall time, respectively, which remove the affects of utilizing the rise and fall times of an ideal simulate signal.

5. The method of claim 4, wherein Trise=(RFC₁ +RFC₂ *CL_IN)*DF_n-1 ;

Tfall=(RFC₃ +RFC₄ *CL_IN)*DF_n-1 ; and

wherein RFC₁ through RFC₄ are coefficients which correspond to the rise and fall times of the signal traversing the input pin of the cell;

CL_IN is the total capacitive load on the input pin of the cell; and

DF_n-1 is the total propagation delay derating factor of a cell which interfaces the cell at the input pin.

6. The method of claim 1, wherein the rising and falling edge delay correction factors which correspond to the rising and falling edges of a signal traversing an either path for which an active edge of said cell is known comprise, respectively,

MAX [0, MCLH*(Tactive_-- edge-Krise)] and

MAX [0, MCHL*(Tactive_-- edge-Kfall)];

and

wherein the MAX function selects the highest one of the values separated by commas and located within square brackets;

MCLH and MCHL are the input rise time sensitivity factor and the input fall time sensitivity factor, respectively, which measure the effect on the cell of the slew rate of the signal traversing the input pin of the cell;

Tactive_-- edge is the rise time and the fall time, respectively, at the active edge of the input pin of the cell; and

Krise and Kfall are the standard rise time and standard fall time, respectively, which remove the effect of utilizing the rise and fall times of an ideal simulated signal.

7. The method of claim 6, wherein Tactive_-- edge=RFC₅ +RFC₆ *CL_IN)*DF_n-1 ;

and wherein RFC₅ and RFC₆ are coefficients which correspond to the rise and fall time of the signal traversing the input pin of the cell;

CL_IN is the total capacitive load on the input pin of the cell; and

DF_n-1 is the total propagation delay derating factor of a cell which interfaces the cell at the input pin.

8. A method of determining a delay time of a signal through a logic cell which interfaces with one or more other logic cells, said logic cell having at least one input pin and at least one output pin, the method comprising the steps of:

providing input data characteristic of the logic cell, said data including cell type, total capacitive load at said at least one input pin, total capacitive load at said at least one output pin, and slew rate of a simulated signal applied to said at least one input pin;

providing a database of predetermined library cell data including base delay computation factors and sensitivity factors for a range of library cell types;

determining from said library cell data and said input data at least on edge delay base factor which approximates the delay time of the associated edge of a signal through the logic cell, said associated edge associated with a corresponding edge of said simulated signal, the delay time being selected from at least one of a rising edge time associated with the rising edge of the signal and a falling edge delay time associated with the falling edge of the signal and wherein the respective edge delay times are obtained for the associated edges of the signal;

calculating an edge delay correction factor based substantially upon the slew rate of the corresponding edge of said simulated signal applied to at least one input pin of said cell and upon the capacitance load at said at least one output pin; and

adding the edge delay base factor to the corresponding edge delay correction factor to determine the delay time.

9. The method of claim 8, wherein the rising and falling edge delay correction factors which correspond to the rising and falling edges of a signal traversing a non-inverting path comprise, respectively, MAX [0, MCLH_C *(Trise_c -Krise)] and MAX [0, MCHL_c *(Tfall_c -Kfall)];

and

wherein the MAX function selects the highest one of the values separated by commas and located within square brackets;

MCLH_c and MCHL_c are the input rise time sensitivity factor and the input fall time sensitivity factor, respectively, which measure the effect upon said cell of the slew rate of the signal traversing the input pin of said cell and the effect of the capacitance load;

Trise_c and Tfall_c represent the rise time and fall time, respectively, at the input pin of said cell; and

Krise and Kfall are the standard rise time and the standard fall time, respectively, which remove the effects of utilizing the rise and fall times of an ideal simulated signal.

10. The method of claim 9, wherein Trise=(RFC₁,c +RFC₂,c *CL_IN)*DF_n-1 ;

Tfall=(RFC₃,c +RFC₄,c *CL_IN))*DF_n-1 ; and

wherein RFC₁,c through RFC₄,c are coefficients which correspond to the rise and fall times of the signal traversing the input pin of said cell and also correspond to said capacitance load;

CL_IN is the total capacitive load the input pin of said cell; and

DF_n-1 is the total propagation delay derating factor of a cell which interfaces said cell at the input pin.

11. The method of claim 8, wherein the rising and falling edge delay correction factors which correspond to the rising and falling edges of a signal traversing an inverting path comprise, respectively, MAX [0, MCLH_c *(Tfall_c -Krise)] and MAX [0, MCHL_c *(Trise_c -Kfall)];

and

wherein MAX is a function which selects the highest one of the values separated by commas and located within square brackets;

MCLH_c and MCHL_c are the input rise time sensitivity factor and the input fall time sensitivity factor, respectively, which measure the effect upon said cell of the slew rate of the signal traversing the input pin of said cell and the effect of the capacitance load;

Trise_c and Tfall_c are the rise time and the fall time, respectively, at the input pin of said cell; and

Krise and Kfall are the standard rise time and the standard fall time, respectively, which remove the effects of utilizing the rise and fall times of an ideal simulated signal.

12. The method of claim 11, wherein Trise=(RFC₁,c +RFC₂,c *CL_IN)*DF_n-1 ;

Tfall=(RFC₃,c +RFC₄,c *CL_IN)*DF_n-1 ; and

wherein RFC₁,c through RFC₄,c are coefficients which correspond to the rise and fall times of the signal traversing the input pin of said cell and also correspond to said capacitance load;

CL_IN is the total capacitive load the input pin of said cell; and

DF_n-1 is the total propagation delay derating factor of a cell which interfaces said cell at the input pin.

13. The method of claim 8, wherein the rising and falling edge delay correction factors which correspond to the rising and falling edges of a signal traversing an either path for which an active edge of said cell is known comprise, respectively,

MAX [0, MCLH_c *(Tactive_-- edge_c -Krise)] and

MAX [0, MCHL_c *(Tactive_-- edge_c -Kfall)];

and

wherein the MAX function selects the highest one of the values separated by commas and located within square brackets;

MCLH_c and MCHL_c are the input rise time sensitivity factor and the input fall time sensitivity factor, respectively, which measure the effect upon said cell of the slew rate of the signal traversing the input pin of said cell and the impact of the capacitance load;

Tactive_-- edge_c is the rise time and the fall time, respectively, at the active edge of the input pin of said cell and corresponding to said capacitance load; and

Krise and Kfall are the standard rise time and the standard fall time, respectively, which remove the effects of utilizing the rise and fall times of an ideal simulated signal.

14. The method of claim 13, wherein Tactive_-- edge=(RFC₅,c +RFC₆,c *CL_IN)*DF_n-1 ;

and wherein RFC₅,c and RFC₆,c are coefficients which correspond to the rise and fall times of the signal traversing the input pin of said cell;

CL_IN is the total capacitive load on the input pin of said cell; and

DF_n-1 is the total propagation delay derating factor of a cell which interfaces said cell at the input pin.

15. A method of determining delay time of a signal through a logic cell which interfaces with one or more other logic cells, said logic cell having at least one input pin and at least one output pin and at least one delay path, the method comprising the steps of:

providing input data characteristic of the logic cell, said data including cell type, total capacitive load at said at least one input pin, total capacitive load at said at least one output pin, and slew rate of a simulated signal applied to said at least one input pin;

providing a database of predetermined library cell data including base delay computation factors and sensitivity factors for a range of library cell types;

determinig from said library cell data and said input data an edge delay base factor which approximates the delay time of the associated edge of signal through the logic cell, said associated edge associated with a corresponding edge of said impulse signal, the delay time being selected from a t least one of a rising edge delay time associated with a rising edge of the signal and a falling edge delay time associated with a falling edge of the signal and wherein the respective edge times are obtained for the associated edges of the signal;

calculating an edge delay correction factor based substantially upon the slew rate of the corresponding edge of said simulated signal applied to at least one input pin of said cell, upon the capacitance load at said at least one output pin, and upon the delay path traversed by said signal; and

adding the edge delay base factor tot he corresponding edge delay correction factors, to determine the delay time.

16. The method of claim 15, wherein the rising and falling edge delay correction factors which correspond to the rising and falling edges of a signal traversing a non-inverting path comprise, respectively, MAX [0, MCLH_c,d *(Trise_c,d -Krise)] and MAX [0, MCHL_c,d *(Tfall_c,d -Kfall)];

and

wherein the MAX function selects the highest one of the values separated by commas and located within square brackets;

MCLH_c,d and MCHL_c,d are the input rise time sensitivity factor and the input fall time sensitivity factor, respectively, which measure the effect upon said cell of the slew rate of the signal traversing said at least one input pin of said cell, the effect of said capacitance load, and the effect of said delay path traversed by said signal;

Trise_c,d and Tfall_c,d are the rise time and the fall time, respectively, at the input pin of said cell; and

Krise and Kfall are the standard rise time and the standard fall time, respectively, which remove the effects of utilizing the rise and fall times of an ideal simulated signal.

17. The method of claim 15, wherein the rising and falling edge delay correction factors which correspond to the rising and falling edges of a signal traversing a standard inverting path comprise, respectively, MAX [0, MCLH_c,d *(Tfall_c,d -Krise)] and MAX [0, MCHL_c,d *(Trise_c,d -Kfall)];

and

wherein the MAX function selects the highest one of the values separated by commas and located within square brackets;

MCLH_c,d and MCHL_c,d are the input rise time sensitivity factor and the input fall time sensitivity factor, respectively, which measure the effect upon said cell of the slew rate of the signal traversing the input pin of said cell, the effect of said capacitance load, and the effect of said delay path traversed by said signal;

Trise_c,d and Tfall_c,d are the rise time and the fall time, respectively, at the input pin of said cell; and

Krise and Kfall are the standard rise time and the standard fall time, respectively, which remove the effects of utilizing the rise and fall times of an ideal simulated signal.

18. The method of claim 15, wherein the rising and falling edge delay correction factors which correspond to the rising and falling edges of a signal traversing a standard either path for which an active edge of said cell is known comprise, respectively, MAX [0, MCLH_c,d *(Tactive_-- edge_c,d -Krise)] and MAX [0, MCHL_c,d *(Tactive_-- edge_c,d -Kfall)];

and

wherein the MAX function selects the highest one of the values separated by commas and located within square brackets;

MCLH_c,d and MCHL_c,d are the input rise time sensitivity factor and the input fall time sensitivity factor, respectively, which measure the effect upon the cell of the slew rate of the signal traversing said at least one input pin of said cell, the effect of said capacitance load, and the effect of said delay path traversed by said signal;

Tactive_-- edge_c,d are the rise time and the fall time, respectively, at the active edge of the input pin of said cell; and

Krise and Kfall are the standard rise time and the standard fall time, respectively, which remove the effects of utilizing the rise and fall times of an ideal simulated signal.

19. The method of claim 16, wherein Trise=(RFC₁,c,d +RFC₂,c,d *CL_IN)*DF_n-1 ;

Tfall=(RFC₃,c,d +RFC₄,c,d *CL_IN)*DF_n- ;

wherein RFC₁,c,d through RFC₄,c,d are coefficients which correspond to, respectively, the rise and the fall times of the signal traversing said at least one input pin of said cell, said capacitance load, and said delay path traversed by said signal;

wherein CL_IN is the total capacitive load on said at least one input pin of said cell; and

wherein DF_n-1 is the total propagation delay derating factor of a cell which interfaces said cell at its said at least one input pin.

20. The method of claim 17, wherein Trise=(RFC₁,c,d +RFC₂,c,d * CL_IN )* DF_n-1 ;

Tfall= (RFC₃,c,d +RFC₄,c,d *CL_iN)*DF_n-1 ;

wherein RFC₁,c,d through RFC₄,c,d are coefficients which correspond to, respectively, the rise and the fall times of the signal traversing said at least one input pin of said cell, said capacitance load, and said delay path traversed by said signal;

wherein CL_IN is the total capacitive load on said at least one input pin of said cell; and

wherein DF_n-1 is the total propagation delay derating factor of a cell which interfaces said cell at its said at least one input pin.

21. The method of claim 18, wherein Tactive_-- edge=(RFC₅,c +RFC₆,c *Cl_IN)*DF_n-1 ;

wherein RFC₅,c,d and RFC₆,c,d are coefficients which correspond to, respectively, the rise and the fall times of the signal traversing said at least one input pin of said cell, said capacitance load, and said delay path traversed by said signal;

CL_IN is the total capacitive load on said at least one input pin of said cell; and

wherein DF_n-1 is the total propagation delay derating factor of a cell which interfaces said cell at its said at least one input pin.

22. In the process of designing and fabricating an integrated circuit using a cell library, the steps of:

determining an initial cell design;

emulating a delay time for the initial cell design;

further developing the cell design; and

, prior to fabricating an integrated circuit containing the cell, emulating a delay time for the developed cell, each emulation step comprising determining an edge delay base factor which approximates the delay time of at least one of the rising edge and the falling edge of a signal through the logic cell;

calculating an edge delay correction factor based substantially upon the slew rate of the signal applied to at least one input pin of the cell; and

adding the edge delay base factor to the corresponding edge delay correction factor to emulate the delay time.

23. The process of claim 22, wherein the edge delay correction factor is base substantially upon said slew rate and upon the capacitance load at an output pin of the cell.

24. The process of claim 23, wherein the edge delay correction factor is based upon said slew rate and said capacitance load and further upon the delay path traversed by the signal.