Circuit and method for normalizing detector circuit

• US 5,274,578 A
• Filed: 03/12/1992
• Issued: 12/28/1993
• Est. Priority Date: 11/30/1989
• Status: Expired due to Term

• Current Assignee: DRS RSTA Incorporated (Leonardo S.p.A.)
• Original Assignee: Texas Instruments, Inc.
• Inventors: Robertson, James E., Mortland, Glenn T., Noeth, Jon C., Box, David O., Zumwalt, Terry L.
• Primary Examiner(s): Black, Thomas G.
• Assistant Examiner(s): ZANELLI, MICHAEL J
• Application Number:
  US07/850,255
• Time in Patent Office: 656 Days
• Field of Search: 364/582, 364/575, 364/574, 364/571.02, 364/571.04, 364/571.01, 364/572, 364/557, 358/113, 250/330, 250/332, 250/334
• US Class Current: 702/99
• CPC Class Codes: G01D 18/006 Intermittent recalibration
• CPC Class Codes: G01D 3/022 having an ideal characteristic, map or correction data stored in a digital memory
• CPC Class Codes: H04N 25/21 for transforming thermal infrared radiation into image signals
• CPC Class Codes: H04N 25/673 by using reference sources
• CPC Class Codes: H04N 5/33 Transforming infrared radiation cameras or camera modules for generating image signals from infrared radiation H04N23/20; circuitry of SSIS for transforming infrared radiation into image signals H04N25/20

Abstract

A dynamic detector normalization circuit for normalizing detector output data using detector-error-correcting offset and gain coefficients that are updated in real time. The offset/gain coefficients are computed by a coefficient processor (20) at selected update intervals based on detector responses to a reference source. The coefficient processor averages detector reference responses over a number of update intervals to obtain updated offset/gain coefficients with greater precision than that available from the detector network. The detector normalization circuit (10) includes offset addition logic (12) and gain coefficient logic (14) for reading-out the offset/gain coefficients stored in respective RAMs (13, 15). For each detector output sample received by the detector normalization circuit (10), an offset addition operation 40 adds to the sample the MS bits of the offset coefficient. After the addition operation, the LS bits of the offset coefficient (representing increased precision available from the offset coefficient) are concatenated, and after underflow/overflow protection (42), an offset-corrected detector sample is obtained. A gain multiplication operation (50) multiplies the offset-corrected detector sample by the gain coefficient to obtain an offset/gain-corrected detector sample. After discarding LS bits representing unnecessary precision, and range-clipping (60), the normalization circuit (10) outputs normalized detector data with the desired precision. The detector normalization technique is described in connection with an exemplary application for normalizing thermal detector array output in a thermal imaging system.

Claims

1. A normalization system for normalizing detector output signals from a detector, comprising:

reference means for causing the detector to detect a reference source at selected update intervals, such that the detector generates corresponding detector reference signals that exhibit offset and gain errors representative of the detector output;

a coefficient processor that, each update interval, is responsive to said reference signals for generating corresponding offset and gain coefficients that respectively correct offset and gain errors in said reference signals;

said coefficient processor computing gain and offset coefficients with greater precision than the precision of the detector output signals;

offset addition logic synchronized with the detector output signals for adding to each detector output signal said corresponding offset coefficient to obtain an offset value;

gain multiplication logic synchronized with the detector output signals for multiplying the offset value by said corresponding gain coefficient; and

synchronization logic for synchronizing said offset addition and gain multiplication operations;

such that the normalization system outputs a normalized detector signal with greater precision than the detector output signal received by the normalization system, and for which offset and gain errors are corrected in accordance with the normalization function represented by said offset and gain coefficients.

2. The normalization system of claim 1, wherein the detector is an array of multiple detectors, and wherein:

for each update interval, each detector generates a corresponding reference signal that exhibits associated gain and offset errors;

for each update interval, said coefficient processor generates for each detector corresponding gain and offset coefficients; and

for each detector, said offset addition and gain multiplication logic are synchronized with the detector array output signals to perform respective offset addition and gain multiplication operations using the corresponding offset and gain coefficients for each detector.

3. The normalization system of claim 2, further comprising:

coefficient logic for storing said offset and gain coefficients for each detector, and for providing said coefficients to said offset addition and gain multiplication logic in synchronism with the detector output signals received by the normalization system;

said coefficient processor providing updated offset and gain coefficients for each detector to said coefficient logic each time such coefficients are computed in response to detector reference signals output by the detectors during an update interval.

4. The normalization system of claim 3, further comprising:

addressing logic for providing coefficient addresses for corresponding offset and gain coefficients in synchronism with the detector output signals;

said coefficient logic being responsive to said coefficient addresses to provide said offset and gain coefficients.

5. The normalization system of claim 4, wherein said coefficient logic comprises:

offset coefficient logic, including offset coefficient storage for storing said offset coefficients, for providing said stored offset coefficients to said offset addition logic; and

gain coefficient logic, including gain coefficient storage for storing said gain coefficients, for providing said stored gain coefficients to said gain multiplication logic.

6. The normalization system of claim 1, wherein said coefficient processor computes offset and gain coefficients by averaging detector reference signals from a selected number of update intervals, using the result of such averaging to filter noise and increase signal-to-noise ratio, thereby enabling said coefficient processor to compute said offset and gain coefficients with greater precision than the detector output signals.

7. The normalization system of claim 6, wherein, after offset addition and gain multiplication, data bits representing unnecessary precision are discarded, providing an output normalized detector signal of a selected precision.

8. A thermal detector normalization system for normalizing detector output signals from an array of thermal radiation detectors, comprising:

reference means for causing the detectors of the array to detect at least two thermal reference sources at selected update intervals, such that each detector generates corresponding detector reference signals that exhibit offset and gain errors representative of detector output;

a coefficient processor responsive each update interval to said reference signals for generating corresponding offset and gain coefficients for each detector that respectively correct offset and gain errors in said reference signals;

said coefficient processor computing gain and offset coefficients with greater precision than the precision of the detector output signals;

offset addition logic synchronized with the detector output signals for adding to each detector output signal said corresponding offset coefficient; and

gain multiplication logic synchronized with the detector output signals for multiplying each detector output signal by said corresponding gain coefficient;

such that the normalization system outputs a normalized detector signal for each detector with greater precision than the detector output signal received by the normalization system, and for which offset and gain errors being corrected in accordance with the normalization function represented by said offset and gain coefficients.

9. The thermal detector normalization system of claim 8, further comprising:

coefficient logic for storing said offset and gain coefficients for each detector and for providing those coefficients to said offset addition and gain multiplication logic in synchronism with the detector output signals received by the thermal detector normalization system;

said coefficient processor providing updated offset and gain coefficients for each detector to said coefficient logic each time such coefficients are computed in response to detector reference signals output by the detectors during an update interval.

10. The thermal detector normalization system of claim 9, further comprising:

addressing logic for providing coefficient addresses for corresponding offset and gain coefficients in synchronism with the detector output signals;

said coefficient logic being responsive to said coefficient addresses to provide said offset and gain coefficients.

11. The thermal detector normalization system of claim 10, wherein said coefficient logic comprises:

offset coefficient logic, including offset coefficient storage for storing said offset coefficients, for providing said stored offset coefficients to said offset addition logic; and

gain coefficient logic, including gain coefficient storage for storing said gain coefficients, for providing said stored gain coefficients to said gain multiplication logic.

12. The thermal detector normalization system of claim 8, wherein said coefficient processor computes offset and gain coefficients by averaging detector reference signals for each detector over a selected number of update intervals, using the result of such averaging to filter noise and increase signal-to-noise ratio for the detector reference signals, thereby enabling said coefficient processor to compute said offset and gain coefficients with greater precision than the detector output signals.

13. The thermal detector normalization system of claim 12, wherein, after offset addition and gain multiplication, data bits representing unnecessary precision are discarded, providing an output normalized detector signal of a selected precision.

14. A method of detecting selected phenomena for normalizing detector output from a detector, comprising:

(a) detecting a reference source with a detector at selected update intervals;

(b) generating detector reference signals from the detector at the selected update intervals that exhibit offset and gain errors representative of detector output;

(c) transmitting the detector reference signals to a coefficient processor;

(d) in response to said reference signals generated at each update interval, computing corresponding offset and gain coefficients in the coefficient processor for the detector with greater precision than the precision of the detector output signals that respectively correct offset and gain errors in said reference signals;

(e) adding in adding circuitry to each detector output signal said corresponding offset coefficient to obtain an offset value; and

(f) multiplying the offset value by said corresponding gain coefficient in a multiplier to provide a normalized detector signal output from the detection system that has greater precision than the detector output signal, and for which offset and gain errors are corrected in accordance with the normalization function represented by said offset and gain coefficients.

15. The method of detector normalization of claim 14, wherein the detector is an array of detectors, further comprising the steps:

storing offset and gain coefficients for each detector, which are updated each update interval;

providing such coefficients for offset addition and gain multiplication in synchronism with the detector output signals.

16. The method of detector normalization of claim 15, further comprising the step:

providing coefficient addresses for corresponding offset and gain coefficients in synchronism with the detector output signals;

and gain coefficients being provided in response to said coefficient addresses.

17. The method of detector normalization of claim 14, wherein the step of computing offset and gain coefficients comprises the steps:

averaging detector reference signals for the detector from a selected number of update intervals;

using the result of such averaging to filter noise and increase signal-to-noise ratio for the detector; and

computing said corresponding offset and gain coefficients with greater precision than the detector output signals.

18. The method of detector normalization of claim 17, further comprising the step:

after offset addition and gain multiplication, discarding data bits representing unnecessary precision, and providing an output normalized detector signal of a selected precision.