Large capacity solid-state memory
First Claim
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1. Large capacity solid-state memory apparatus which is digitally addressable by an n-bit code including error-correction bits, comprising:
- a plurality of n large-area memory devices operated in parallel, each comprising a multiplicity of active matrices of memory cells fabricated in a continuous process on a thin, flexible elongate substrate which is much longer than it is wide, a respective matrix of each memory device for storing a respective one of the n bits of digital information required to represent a numbered storage frame thereby to minimize correlation of errors due to manufacturing defects and make it possible for error-correcting codes to provide a high-yield memory in the presence of a reasonable level of defects, address circuit means for addressing said matrices sequentially by frame umber at a selected clock rate and output circuit means including serial-to-parallel multiplexer means for producing at said selected clock rate a one-bit output corresponding to said respective one bit, whereby the effective clock rate of said memory apparatus is n times said selected clock rate.
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Abstract
A large capacity, solid-state memory device is disclosed in which information is stored in a plurality of large-area arrays of memory cells, each of which is a crossed-wire matrix of memory cells fabricated in a continuous process on a thin flexible substrate, using thin film transistor technology, to form an elongate tape. The plurality of tapes are assembled into a compact package by winding them, one upon the other, into a spool, which is placed in a suitable housing which for apparatus having a storage capacity of one terabit has a volume of about 100 cubic inches.
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Citations
10 Claims
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1. Large capacity solid-state memory apparatus which is digitally addressable by an n-bit code including error-correction bits, comprising:
a plurality of n large-area memory devices operated in parallel, each comprising a multiplicity of active matrices of memory cells fabricated in a continuous process on a thin, flexible elongate substrate which is much longer than it is wide, a respective matrix of each memory device for storing a respective one of the n bits of digital information required to represent a numbered storage frame thereby to minimize correlation of errors due to manufacturing defects and make it possible for error-correcting codes to provide a high-yield memory in the presence of a reasonable level of defects, address circuit means for addressing said matrices sequentially by frame umber at a selected clock rate and output circuit means including serial-to-parallel multiplexer means for producing at said selected clock rate a one-bit output corresponding to said respective one bit, whereby the effective clock rate of said memory apparatus is n times said selected clock rate. - View Dependent Claims (2, 3, 4, 5, 6)
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7. Large capacity solid-state memory apparatus comprising:
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a plurality of large-area memory devices adapted to be operated in parallel each comprising a multiplicity of active matrices of memory cells fabricated on a thin, flexible elongate substrate much longer than it is wide, said plurality of elongate substrates being wound one upon the other into a compact cylindrical spool, a respective matrix of each of said memory devices being adapted to store a respective one of the number of bits required to represent a numbered storage frame; address circuit means coupled to said matrices for addressing said matrices sequentially by frame number at a selected clock rate; and output circuit means coupled to said matrices and including serial-to-parallel multiplexer means for producing a one-bit output from each large-area memory device corresponding to said respective one bit, at said selected clock rate, whereby the effective clock rate of said memory apparatus is substantially said selected clock rate multiplied by the number of large-area memory devices. - View Dependent Claims (8, 9, 10)
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Specification