Large capacity solid-state memory

• US 5,274,602 A
• Filed: 10/22/1991
• Issued: 12/28/1993
• Est. Priority Date: 10/22/1991
• Status: Expired due to Fees

• Current Assignee: Iowa State University Research Foundation Incorporated (Iowa State University)
• Original Assignee: Florida Atlantic University (State University System of Florida)
• Inventors: Glenn, William E.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): TRAN, ANDREW Q
• Application Number:
  US07/780,248
• Time in Patent Office: 798 Days
• Field of Search: 365/189.02, 365/200, 365/221, 365/230.09, 365/239, 365/230.01, 257/54, 257/57, 257/73, 257/60, 257/66, 257/315, 257/316, 257/318, 257/319, 257/320, 257/321, 257/702
• US Class Current: 365/239
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 438/907 Continuous processing

Abstract

A large capacity, solid-state memory device is disclosed in which information is stored in a plurality of large-area arrays of memory cells, each of which is a crossed-wire matrix of memory cells fabricated in a continuous process on a thin flexible substrate, using thin film transistor technology, to form an elongate tape. The plurality of tapes are assembled into a compact package by winding them, one upon the other, into a spool, which is placed in a suitable housing which for apparatus having a storage capacity of one terabit has a volume of about 100 cubic inches.

Claims

1. Large capacity solid-state memory apparatus which is digitally addressable by an n-bit code including error-correction bits, comprising:

a plurality of n large-area memory devices operated in parallel, each comprising a multiplicity of active matrices of memory cells fabricated in a continuous process on a thin, flexible elongate substrate which is much longer than it is wide, a respective matrix of each memory device for storing a respective one of the n bits of digital information required to represent a numbered storage frame thereby to minimize correlation of errors due to manufacturing defects and make it possible for error-correcting codes to provide a high-yield memory in the presence of a reasonable level of defects, address circuit means for addressing said matrices sequentially by frame umber at a selected clock rate and output circuit means including serial-to-parallel multiplexer means for producing at said selected clock rate a one-bit output corresponding to said respective one bit, whereby the effective clock rate of said memory apparatus is n times said selected clock rate.

2. Memory apparatus according to claim 1, wherein said plurality of elongate substrates are wound one upon the other into a compact cylindrical spool.

3. Memory apparatus according to claim 1, wherein each memory cell is a floating gate memory fabricated in a continuous lithographic process using thin film transistor technology.

4. Memory apparatus according to claim 1, wherein each memory cell is a floating-gate tunnel oxide MOS one-bit cell fabricated in a continuous lithographic process using thin film transistor technology.

5. Memory apparatus according to claim 1 utilizing 10-bit encoding, wherein said apparatus comprises ten large-area memory devices operated in parallel, and

wherein said address circuit addresses said matrices at a clock rate of about 1 MHz.

6. Memory apparatus according to claim 2, wherein each large-area memory device is in the form of an elongate tape about four inches (ten cm.) wide and thirty microns thick, and wherein said tapes each has a length and said arrays of memory cells have a density such as to provide a storage capacity of about one terabit in a spool having a diameter of about five inches.

7. Large capacity solid-state memory apparatus comprising:

a plurality of large-area memory devices adapted to be operated in parallel each comprising a multiplicity of active matrices of memory cells fabricated on a thin, flexible elongate substrate much longer than it is wide, said plurality of elongate substrates being wound one upon the other into a compact cylindrical spool, a respective matrix of each of said memory devices being adapted to store a respective one of the number of bits required to represent a numbered storage frame;

address circuit means coupled to said matrices for addressing said matrices sequentially by frame number at a selected clock rate; and

output circuit means coupled to said matrices and including serial-to-parallel multiplexer means for producing a one-bit output from each large-area memory device corresponding to said respective one bit, at said selected clock rate, whereby the effective clock rate of said memory apparatus is substantially said selected clock rate multiplied by the number of large-area memory devices.

8. Memory apparatus according to claim 7, having a plurality of n large-area memory devices, wherein a respective matrix of each memory device is adapted to store a respective bit of information required to represent a numbered frame whereby to minimize correlation of errors due to manufacturing defects.

9. Memory apparatus according to claim 8, wherein each memory cell is a floating gate one-bit cell fabricated in a continuous lithographic process using thin film transistor technology.

10. Memory apparatus according to claim 8, wherein said address circuit means is adapted to address said matrices with an n-bit code including error-correcting bits, and wherein said selected clock rate is about 1 MHz.