Optimized clock recovery for an MSK system

• US 5,274,672 A
• Filed: 10/31/1991
• Issued: 12/28/1993
• Est. Priority Date: 10/31/1991
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Weiss, Karl R.
• Primary Examiner(s): Kuntz, Curtis
• Assistant Examiner(s): GHEBRETINSAE, TEMESGHEN
• Application Number:
  US07/785,963
• Time in Patent Office: 789 Days
• Field of Search: 375/47, 375/64, 375/90, 375/106, 375/113, 375/84, 332/100, 329/300, 455/218, 455/222
• US Class Current: 375/274
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/027 extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
• CPC Class Codes: H04L 7/04 Speed or phase control by synchronisation signals H04L7/0075 takes precedence

Abstract

A clock recovery system for radio communication inserts a synchronization signal (102) at a frequency of 1/2 the baud rate, at the spectral null of an MSK data signal (108), which is also at 1/2 the baud rate, for later retrieval. Hence, in a transmitter-encoder (100), an MSK generator (106) generates an MSK digitally modulated data signal (108e) having a baud rate and a spectral null at 1/2 the baud rate. A synchronization clock generator (104) generates a synchronization signal (102e) having a frequency at 1/2 the baud rate. This frequency at 1/2 the baud rate corresponds to the spectral null of the MSK digitally modulated data signal (108e). A transmitter transmits the synchronization signal (102e), at the spectral null of the data signal (108e), together (112) with the MSK digitally modulated data signal (108e). On the other end, a receiver-decoder (200) recovers (214) the synchronization signal (102d) and demodulates (212) the MSK digitally modulated data signal (108d) as a function of the synchronization signal (102d).

Claims

1. An MSK encoder-transmitter comprising:

MSK generating means for generating an MSK digitally modulated data signal having a bit rate (f_b), the MSK digitally modulated data signal so modulated with binary information as to inherently produce a spectral null (f_n) in its audio frequency spectrum at 1/2 the bit rate, wherein f_n =f_b /2, the data signal containing binary data, having a bit edge occurring at the bit rate, each bit represented by one of two signaling tones, representing a mark or a space, with a plurality of successive bit edges occurring after each bit period (T_b =1/f_b), whereby each of the bit edges occurs at the rate f_b ;

means for generating a synchronization signal, in the audio spectrum, having a synchronization frequency (f_s) at 1/2 the bit rate, the frequency at 1/2 the bit rate corresponding to the spectral null of the MSK digitally modulated data signal, wherein f_s =f_b /2, the synchronization signal having two successive zero-crossings for each synchronization period (T_s =1/f_s =2/f_b =2T_b), each of the zero-crossings occurring at every half period (T_s /2=2T_b /2=Tb) of the synchronization period or every full period of the bit period Tb;

means for injecting in the MSK digitally modulated data signal the synchronization signal within the null to provide a composite data signal, composed of the sum of the MSK digitally modulated data signal and the synchronization signal, for use by receivers; and

means for transmitting a radio frequency signal having a radio frequency carrier signal modulated with the composite data signal, wherein the synchronization frequency is not a function of the transmitted radio frequency signal.

2. An MSK decoder-receiver comprising:

MSK receiving means for receiving an MSK digitally modulated data signal at a bit rate (f_b), together with a synchronization signal, having a synchronization frequency (f_s) at a spectral null (f_n) of the data signal, at 1/2 the bit rate, wherein f_n =f_b /2, wherein f_s =f_b /2, wherein f_s =f_b /2, the data signal containing binary data, occurring at the bit rate, each bit represented by one of two signaling tones, representing a mark or a space, with a plurality of successive bit edges occurring after each bit period (T_b =1/f_b), whereby each of the bit edges occurs at the bit rate f_b, and the synchronization signal having two successive zero-crossings for each synchronization period (T_s =1/f_s =2/f_b =2T_b), each of the zero-crossings occurring at every half period (T_s /2=2T_b /2=T_b) of the synchronization period or every full period of the bit period Tb;

means for recovering the synchronization signal to detect a time occurrence of each zero-crossing of the synchronization signal at T_s /2=T_b ; and

bit alignment means for demodulating the MSK digitally modulated data signal as a function of the synchronization signal by referencing the time occurrence of each zero-crossing of the synchronization signal at T_s /2=T_b as one of the successive bit edges of the data signal, whereby the bit between two successive bit edges, occurring during the bit period (T_b) can be sampled to determined whether the tone represents the mark or the space.

3. A clock recovery system for radio communication, the system comprising:

an MSK encoder-transmitter comprising;

MSK generating means for generating an MSK digitally modulated data signal having a bit rate (f_b) and an inherent spectral null (f_n) at 1/2 the bit rate, wherein f_n =f_b /2, the data signal containing binary data, occurring at the bit rate (f_b), each bit represented by one of two signaling tones, having one of two possible values, with a plurality of successive bit edges, occurring after each bit period (T_b =1/f_b);

means for generating a synchronization signal, in the audio spectrum, having a frequency at 1/2 the bit rate, the frequency at 1/2 the bit rate corresponding to the spectral null of the MSK digitally modulated data signal, wherein f_s =f_b /2, the synchronization signal having two successive zero-crossings for each synchronization period (T_s =1/f_s =2/f_b =2T_b), each of the zero-crossings occurring at every half period (T_s /2=2T_b /2=T_b) of the synchronization period or every full period of the bit period Tb; and

means for transmitting the synchronization signal, at the spectral null of the data signal, together with the MSK digitally modulated data signal, at the bit rate, to compose a composite MSK digitally modulated data signal for modulating a radio frequency signal that is to be transmitted, wherein the frequency of the synchronization signal, f_s =f_b /2, is not a function of the transmitted radio frequency signal; and

an MSK receiver comprising;

MSK receiving means for receiving the MSK digitally modulated data signal at the bit rate, together with the synchronization signal at the spectral null of the data signal, at 1/2 the bit rate;

means for recovering the synchronization signal to detect a time occurrence of each zero-crossing of the synchronization signal at T_s /2=T_b ; and

bit alignment means for demodulating the MSK digitally modulated data signal as a function of the synchronization signal by referencing the time occurrence of each zero-crossing of the synchronization signal at T_s /2=T_b as one of the successive bit edges of the data signal, whereby the bit between two successive bit edges, occurring during the bit period (T_b) can be sampled to determine its value.

4. The clock recovery system of claim 3 wherein the means for transmitting includes transmitter filtering means.

5. The clock recovery system of claim 4 further comprises:

delaying means, in the MSK encoder-transmitter, for delaying the synchronization signal, generated by the MSK encoder-transmitter, with respect to the MSK digitally modulated data signal to compensate for the phase distortion of the transmitter filtering means.

6. The clock recovery system of claim 3 wherein the means for receiving includes receiver filtering means comprising:

a notch filter for filtering out the synchronization signal f_s =f_b /2 from the recovered data signal to provide the data bits; and

a bandpass filter, operating around the synchronization frequency to retrieve the synchronization frequency to synchronize the data bits by aligning the zero-crossings of the synchronization signal with the bit edges of the data bits.

7. The clock recovery system of claim 6 further comprising:

delaying means for delaying the synchronization signal, recovered by the MSK receiver, with respect to the MSK digitally modulated data signal to compensate for the phase distortion of the receiver filtering means.

8. The clock recovery system of claim 3 wherein the means for demodulating comprises a matched filter.

9. The clock recovery system of claim 3 further comprising:

in the MSK receiver;

means for muting an audio speaker means in response to detecting the synchronization signal.

10. The clock recovery system of claim 3 wherein the means for transmitting comprises summing means for summing the synchronization signal and the MSK digitally modulated data signal.