Multifunctional coupler for connecting a central processing unit of a computer to one or more peripheral devices

• US 5,274,765 A
• Filed: 04/17/1990
• Issued: 12/28/1993
• Est. Priority Date: 04/17/1989
• Status: Expired due to Term

• Current Assignee: Bull Sas (Atos SE)
• Original Assignee: Bull Sas (Atos SE)
• Inventors: Le Gallo, Remy
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Chaki, Kakali
• Application Number:
  US07/510,275
• Time in Patent Office: 1,351 Days
• Field of Search: 364/DIG. 1, 364/DIG. 2, 395/275, 395/400
• US Class Current: 710/64
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers

Abstract

A multifunctional coupler for connecting a central processing unit of a computer to one or more peripheral devices and for storing at least one portion of an application microprogram that is operative to control transfer of data between a peripheral and the CPU. The coupler includes a mother-board with at least a first and second interface for connecting an output bus of the CPU to at least first and second daughter-boards, respectively. The mother-board also includes a control and command microprocessor that is connected to both the first and second interfaces, a RAM and a first ROM, all connected to an output bus of the microprocessor. The daughter-boards each include a second ROM for storing an application microprogram that includes a first program segment common to all application microprograms run by the microprocessor, that is read from the first ROM, and a second segment that is read from a second ROM, the second segment being specific to a particular application executed by a peripheral.

Claims

1. A multifunctional coupler for connecting a computer central processing unit (CPU) and a plurality of peripherals, for storing at least one application microprogram, each application program operative to control a transfer of data between a peripheral and the CPU, and for executing each of the at least one application microprograms, the coupler comprising:

a mother-board coupled to at least one daughter-board, the mother-board including;

at least one daughter interface connected to an output bus of the central processing unit;

a control and command microprocessor connected to each of the at least one daughter interfaces;

a random access memory connected to an output bus of said microprocessor; and

a first read-only memory connected to said output bus of said microprocessor, said first read-only memory for storing a first application program segment that is common to each of the at least one application microprograms stored in the multifunctional coupler; and

each daughter-board including;

a second read-only memory for storing a second application program segment of a first one of the at least one application microprograms wherein the second application program segment is for controlling a peripheral connected to the respective daughter-board, and wherein the second application program segment is not executable until it is transferred to said random access memory of said mother-board;

a peripheral interface, connected to said second read-only memory, for connection to a peripheral; and

a mother interface, connected to said second read-only memory, for connection to said mother board;

wherein said control and command microprocessor includes a transfer means for transferring the second application program segment of the first one of the at least one application microprograms from said second read-only memory to said random access memory of said mother-board;

wherein said transfer means comprises means for shifting addresses of the application microprogram in the second read-only memory so as to render the application microprogram executable in the random access memory; and

means for executing the application microprogram by the CPU after the application microprogram is rendered executable in the random access memory.

2. The coupler of claim 1 wherein said first and second ROMs are erasable programmable ROMs.

3. The coupler of claim 1 wherein said daughter-board further comprises:

an application circuit, connected to said mother interface and to said peripheral interface, said application circuit including;

parity checking circuitry;

screen format checking circuitry; and

protocol consistency-checking circuitry, cooperative with said parity checking circuitry and said screen format checking circuitry,

said application circuit ensuring transmission of information from a peripheral to said mother-board by performing parity checking, screen format checking, and protocol consistency checking.

4. The coupler of claim 1 wherein the application microprogram includes a node microprogram for loading other microprograms, and wherein said node microprogram is stored in said first ROM.

5. A method of operating a multifunctional coupler for coupling a CPU to a plurality of peripherals, the coupler including a mother-board and a plurality of daughter-boards wherein the mother-board includes a control and command microprocessor, a random access memory, and a first read-only memory for storing a first segment of an application microprogram, the first segment being common to each of a plurality of application microprograms for controlling a corresponding plurality of peripherals, wherein each of the daughter-boards includes a second read-only memory for storing a second segment of the application microprogram for controlling a peripheral coupled to each of the daughter-boards wherein the method comprises the steps of:

(a) loading a node microprogram of an application microprogram corresponding to a selected peripheral into the random access memory of the mother-board by the control and command microprocessor;

(b) under control of the node microprogram, loading the first segment of the application microprogram into the random access memory of the mother-board by the control and command microprocessor;

(c) under control of the node microprogram, loading a second segment of the application microprogram from a second read-only memory of a daughter-board into the random access memory of the mother-board, by the control and command microprocessor wherein the step of loading the second segment of the application microprogram includes the steps of;

(i) preparing the random access memory of the mother-board to receive the second segment of the application microprogram from a second read-only memory;

(ii) testing for the presence and correct operation of a first daughter-board of said plurality of daughter-boards;

(iii) if the testing step indicates that the first daughter-board is not present or is not correctly operating, loading the application microprogram from an alternate daughter-board;

(iv) in response to the testing step indicating that the first daughter-board is present and that the first daughter-board is operating correctly, verifying the contents of the second read-only memory on the first daughter-board, wherein the verifying step includes the step of verifying relocation parameters stored in the second read-only memory of the first daughter-board, and if the step of verifying fails, loading the application microprogram from an alternate daughter-board, and if the step of verifying does not fail transferring the contents of the second read-only memory on said first daughter-board into the random access memory of the mother-board;

(v) shifting addresses of the application microprogram int he second read-only memory of the first daughter-board so as to render the application microprogram executable in the random access memory of the mother-board; and

(vi) loading the addresses provided in the shifting step from the read-only memory of the first daughter-board to the random access memory of the mother-board; and

(d) executing the application microprogram by the CPU.

6. The method of claim 5 wherein the step of preparing the RAM includes the steps of:

zeroing a plurality of memory locations in the RAM;

receiving the second segment of the application microprogram from the second ROM into the RAM; and

indicating associated memory addresses int he RAM allocated to the second segment.

7. The method of claim 5 wherein the step of transferring the contents of the second ROM into the RAM takes place at the associated memory addresses.