Flexible host interface controller architecture

• US 5,274,773 A
• Filed: 12/29/1992
• Issued: 12/28/1993
• Est. Priority Date: 11/09/1990
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Conner Peripherals Incorporated (Whitehouse Group Ltd.)
• Inventors: Keeler, Stanton M., Sander, Charles M., Squires, John P., Clay, Donald W.
• Primary Examiner(s): CHUN, DEBRA
• Application Number:
  US07/997,860
• Time in Patent Office: 364 Days
• Field of Search: 395/275, 395/325, 395/425, 340/825.03
• US Class Current: 710/38
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device

Abstract

A high level controller for maintaining communication with a host processor via a host processor interface for establishing communication paths between the host processor interface, an internal processor and a plurality of storage means. A first means receives indicia from the internal processor where the indicia specifies one of the communication paths and generates control signals for forming the specific communication path requested. A second means receives the control signals from the first means and forms the requested communication path. A third means is connected to the first and second means for controlling the communication of the system with the host processor interface in accordance with control signals generated by the first means. In this manner various data paths for communication between the host interface, internal processor and a plurality of storage means may be adaptably specified and formed to make optimum use of the system.

Claims

1. A host interface apparatus in a hard disk drive system connected to a host processor via a host processor interface, said hard disk drive system including a processor, storage media and a plurality of storage channel means for storing data on and retrieving data from said storage media, said host interface apparatus establishing communication paths between said host processor and said processor, between said host processor and each of said storage channel means, between said processor and each of said storage channel means and between said storage channel means, said host interface apparatus comprising:

first means connected to said processor for receiving from said processor indicia specifying a communication path, said communication path being between said host processor and said processor, or between said host processor and one of said storage channel means, or between said processor and one of said storage channel means and or between two of said storage channel means said first means generating control signals in response to said indicia for forming said specified communication path and for the transfer of information along said specified communication path;

second means connected to said first means for forming said specified communication path in said host interface apparatus in response to said control signals received from said first means; and

third means connected to said first and second means for controlling communications between said host processor and said hard disk drive system in response to said control signals generated by said first means.

2. The host interface apparatus of claim 1 wherein said second means further comprises:

fourth means having a plurality of inputs and an output, one said input connected to said third means, one said input connected to said processor and one said input connected to each of said storage channel means, said fourth means in response to said control signals generated by said first means selectively connecting one of said inputs of said fourth means to said output of said fourth means whereby said fourth means selectively provides data received at one of said fourth means inputs to said fourth means output;

fifth means connected to said output of said fourth means for receiving and storing data from said fourth means in response to said control signals generated by said first means, said output of said first means connected to said third means for providing to said third means said data stored in said fifth means to be transferred to said host processor by said third means; and

sixth means connected to said first means, to said output of said fifth means, to said processor, and to each of said storage channel means, said sixth means selectively connecting the said output of said fifth means to one of said storage channel means in response to said control signals received from said first means whereby said sixth means provides a data path for said data stored in said fifth means from said fifth means to one of said storage channel means.

3. The host interface apparatus of claim 2 further comprises:

seventh means having a plurality of inputs and an output selectively connected to said processor in response to control signals generated by said first means, one of said inputs connected to said third means for receiving data transmitted from said host processor, one of said inputs connected to said third means for receiving data to be transferred to said host processor and one of said inputs connected to each of said fifth means output for receiving data to be stored on said storage media via said storage channel means whereby said processor may monitor the transfer of data being transferred along any said communication path created in said host interface apparatus.

4. The host interface apparatus of claim 1 wherein said first means comprises:

control means receiving address and control indicia from said processor for decoding said received indicia and generating said control signals as a function of said indicia so received; and

distributing means connected to said control means for distributing said control signals to form said specified communication path as defined by said indicia from said processor and for controlling the orderly passage of data over said formed selected communication path.

5. The host interface apparatus of claim 2 wherein said first means comprises:

control means receiving address and control indicia from said processor for decoding said received indicia and generating said control signals as a function of said indicia so received; and

distributing means connected to said control means for distributing said control signals to form said specified communication path as defined by said indicia from said processor and for controlling the orderly passage of data over said formed selected communication path.

6. The host interface apparatus of claim 3 wherein said first means comprises:

control means receiving address and control indicia from said processor for decoding said received indicia and generating said control signals as a function of said indicia so received; and

distributing means connected to said control means for distributing said control signals to form said specified communication path as defined by said indicia from said processor and for controlling the orderly passage of data over said formed selected communication path.