Method and system for eliminating operation codes from intermediate prolog instructions
First Claim
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1. A method for operating a computer system, having a processor and a memory, to process Prolog programs having predicates comprising the steps of:
- (a) encoding, using the processor of the computer system, a predicate into a set of instructions stored in the memory of the computer system including a simplified instruction consisting of an address of an object and having preceding instructions;
(b) determining, using the processor of the computer system, an implied operation code for the simplified instruction from the preceding instructions by using a finite state automata having modes for read, write, built and arg to track the preceding instructions and select the implied operation code as unify constant in read and write modes, put constant in built mode and get constant in arg mode; and
(c) executing, using the processor of the computer system, the implied operation code using the address of the object as a parameter.
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Abstract
An improved architecture for a Prolog interpreter is described. Implicit arguments are substituted for classical explicit arguments. The implicit arguments are supported by preassigned register allocation managed by the interpreter. The interpreter also exploits improved Prolog Object processing in which the first bit of the Prolog object word is used as a flag to indicate whether the object word is a type pointer or type descriptor. Significant improvements in interpreter execution result from the usage of these techniques.
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12 Claims
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1. A method for operating a computer system, having a processor and a memory, to process Prolog programs having predicates comprising the steps of:
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(a) encoding, using the processor of the computer system, a predicate into a set of instructions stored in the memory of the computer system including a simplified instruction consisting of an address of an object and having preceding instructions; (b) determining, using the processor of the computer system, an implied operation code for the simplified instruction from the preceding instructions by using a finite state automata having modes for read, write, built and arg to track the preceding instructions and select the implied operation code as unify constant in read and write modes, put constant in built mode and get constant in arg mode; and (c) executing, using the processor of the computer system, the implied operation code using the address of the object as a parameter. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A computer system, having a processor and a memory, for processing Prolog programs having predicates comprising:
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(a) means for encoding, using the processor of the computer system, a predicate into a set of instructions stored in the memory of the computer system including a simplified instruction consisting of an address of an object and having preceding instructions; (b) means for determining, using the processor of the computer system, an implied operation code for the simplified instruction from the preceding instructions using a finite state automata having modes for read, write, built and arg to track the preceding instructions and select the implied operation code as unify constant in read and write modes, put constant in built mode and get constant in arg mode; and (c) means for executing, using the processor of the computer system, the implied operation code using the address of the object as a parameter. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification