Transparent system interrupts with automated input/output trap restart

• US 5,274,826 A
• Filed: 04/26/1993
• Issued: 12/28/1993
• Est. Priority Date: 08/30/1991
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kardach, James, Sivamani, Kameswaran, Nguyen, Cau
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US08/053,960
• Time in Patent Office: 246 Days
• Field of Search: 364/DIG. 1, 364/DIG. II, 395/725
• US Class Current: 710/260
• CPC Class Codes: G06F 9/463 Program control block organisation
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

A CPU of a microprocessor system is modified to post an executed write I/O instruction upon completion of writing by the bus unit. A dedicated memory area is provided for storing a customizable system interrupt service routine, program state data at the time of interruption and an I/O trap indicator indicating the CPU was interrupted during execution of an I/O instruction. The dedicated memory area is normally not mapped as part of the main memory space, thereby keep it inaccessible to the operating system and applications. An unmaskable system supervisor interrupt having higher priority than all other maskable and unmaskable interrupts is added to the CPU interrupts. A RESUME instruction is added to the CPU instructions to provide recovery of the CPU to the state before it was interrupted and continued execution including automatic re-execution of an interrupted I/O instruction. As a result, a system integrator or OEM may provide transparent system level interrupts with automated I/O trap restart that will operate reliably in any operating environment, and be relieved of the heavy burden of managing I/O trap restart.

Claims

1. An improved microprocessor system comprising a central processing unit (CPU) coupled to at least one memory unit and at least one bus unit for executing an operating system and at least one application program comprising a plurality of said CPU'"'"'s instructions, said CPU further having at least two modes of program execution, a real mode and a protected mode, and at least one interrupt for interrupting program execution, wherein the improvement to said microprocessor system comprises:

(a) said CPU waiting until said at least one bus unit has finished executing a write input-output (I/O) instruction before executing a next instruction, said CPU instructions comprising at least one I/O instruction including said write I/O instruction;

(b) said memory units having a dedicated memory area for storing an interrupt processing program, processor state data of said CPU, and an I/O trap indicator,

said dedicated memory area being not mapped as part of main memory space thereby keeping said dedicated memory area inaccessible to said operating system and application programs,

(c) means in response to said interrupt processing program for determining if said CPU is being interrupted during one of said I/O instructions and conditionally setting said I/O trap indicator to indicate said CPU being interrupted during one of said I/O instructions and said interrupted I/O instruction is to be restarted when said CPU resumes execution;

(d) register means comprising an instruction pointer, a prior instruction pointer, and at least one I/O parameter, said instruction and prior instruction pointers pointing to a first and second instructions of said operating system and application programs'"'"' instructions, said first instruction being an instruction to be executed next by said CPU, said second instruction being an instruction just executed by said CPU, said at least one I/O parameter being associated with the most recently executed I/O instruction;

said I/O trap indicator indicating whether said CPU is interrupted during execution of one of said I/O instructions;

(e) System Supervisor Interrupt (SSI) means for interrupting execution of said operating system and said application programs, switching in and mapping said dedicated memory area to a pre-determined segment of said main memory space, storing said processor state data of said CPU into said dedicated memory area, switching said CPU into said real mode of execution, and starting execution of said interrupt processing program, said SSI being unmaskable by said operating system and said application programs, and having a higher priority than other interrupts;

(f) Resume means for restoring said saved processor state data from said dedicated memory area to said CPU, checking said I/O trap indicator to determine if it is set, conditionally decrementing said restored instruction pointer to said restored prior instruction pointer if said I/O trap indicator is set, loading said restored at least one I/O parameter into at least one general purpose register of said CPU, switching out and unmapping said dedicated memory area to said main memory space, and resuming execution of said operating system and said application programs;

thereby allowing said CPU to be interrupted reliably and automated I/O trap restart be provided to said interrupt service program in a manner transparent to said operating system and said application programs.

2. The improved microprocessor system as set forth in claim 1, wherein said memory units comprises on-board random access memory (RAM), and said dedicated memory area is part of said on-board RAM.

3. The improved microprocessor system as set forth in claim 1, wherein said memory units comprises off-board RAM coupled to an on-board RAM controller, and said dedicated memory area is part of said off-board RAM.

4. The improved microprocessor system as set forth in claim 1, wherein said CPU comprises interrupt means for triggering said interrupts including said SSI, said SSI being triggered upon receipt of an electrical signal, said interrupt means comprising an interface for receiving said electrical signal.

5. The improved microprocessor system as set forth in claim 4, wherein said interface is an external circuit pin.

6. The improved microprocessor system as set forth in claim 4, wherein said microprocessor system further comprises an event detection means coupled to at least one system asset of said microprocessor system and said interrupt means for detecting a pre-determined event associated with said system asset and generating for said interface said electrical signal upon said detection.

7. The improved microprocessor system as set forth in claim 1, wherein said CPU comprises instruction means for executing said instructions including said I/O instructions and said Resume instruction.

8. In a microprocessor system comprising a central processing unit (CPU) coupled to at least one memory unit and a bus unit for executing an operating system and at least one application program comprising a plurality of said CPU'"'"'s instructions, said CPU further having at least two modes of program execution, a real mode and a protected mode, and at least one interrupt for interrupting program execution, a method for reliably interrupting said CPU and providing automated I/O trap restart in a manner transparent to said operating system and application programs comprising the steps of:

(a) storing an interrupt processing program in a dedicated memory area on said memory units, said dedicated memory area being not mapped as part of main memory space thereby keeping said dedicated memory area inaccessible to said operating system and application programs;

(b) waiting until said at least one bus unit has finished executing an write input-output (I/O) instruction before executing a next instruction, said instructions comprising at least one I/O instruction including said write I/O instruction;

(c) interrupting execution of said operating system and said application programs upon receipt of a pre-determined input, said interruption being unmaskable by said operating system and said application programs, and having a higher priority than other interruptions;

(d) switching in and mapping said dedicated memory area to a pre-determined segment of said main memory space;

(e) storing processor state data of said CPU into said dedicated memory area, said processor state data comprising an instruction pointer, a prior instruction pointer, and at least one I/O parameter register,

said instruction and prior instruction pointers pointing to a first and second instructions of said operating system and application programs, said first instruction being an instruction to be executed next by said CPU, said second instruction being an instruction just executed by said CPU, said I/O parameter registers being associated with the most recently executed I/O instruction;

(f) switching said CPU into said real mode of execution;

(g) determining if said CPU is being interrupted during execution of one of said I/O instructions, and if said CPU is being interrupted during execution of one of said I/O instructions, and, said interrupted I/O instruction is to be re-executed when said CPU resumes execution, storing said I/O trap indicator in said dedicated memory area;

(h) starting execution of said interrupt processing program;

(i) restoring said saved processor state data, said restoration being controlled by said interrupt service program;

(j) determining if said saved I/O trap indicator is set, and if said saved I/O trap indicator is set, decrementing said restored instruction pointer to said restored prior instruction pointer, and restoring said I/O parameter registers;

(k) switching out and unmapping said dedicated memory area to said main memory space; and

(l) resuming execution of said operating system and said application programs at the instruction pointed to by said instruction pointer.

9. The method as set forth in claim 8, wherein said memory units comprises on-board random access memory (RAM), and said dedicated memory area is part of said on-board RAM.

10. The method as set forth in claim 8, wherein said memory units comprises off-board RAM coupled to an on-board RAM controller, and said dedicated memory area is part of said off-board RAM.

11. The improved microprocessor system as set forth in claim 8, wherein said steps (c) through (h) are performed by interrupt means of said CPU upon receipt of an electrical signal, said interrupt means comprising an interface for receiving said electrical signal.

12. The method as set forth in claim 11, wherein said interface is an external circuit pin.

13. The method as set forth in claim 11, wherein said electrical signal being generated and provided to said interface by an event detection means coupled to at least one system asset of said microprocessor system and said interrupt means upon detection of a pre-determined event associated with said system asset.

14. The method as set forth in claim 11, wherein said steps (b) and steps (i) through (l) are performed by instruction means of said CPU.