Method of forming insulated gate field-effect transistors

• US 5,275,961 A
• Filed: 07/16/1992
• Issued: 01/04/1994
• Est. Priority Date: 11/23/1990
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Smayling, Michael C., Reynolds, Jack
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): NGUYEN, TUAN H
• Application Number:
  US07/915,036
• Time in Patent Office: 537 Days
• Field of Search: 437/41, 437/43, 437/44, 437/45, 437/46, 437/913, 437/52, 437/56, 437/57, 148/DIG. 82
• US Class Current: 438/286
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/405 Resistive arrangements, e.g. resistive or semi-insulating field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66272 Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 : Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: Y10S 148/009 : Bi-MOS
• CPC Class Codes: Y10S 148/082 : Ion implantation FETs/COMs

Abstract

An insulated-gate field-effect transistor (426, 452) has reduced gate oxide stress. According to one embodiment, the control gate (458) has a doped region (460) adjacent the source end of the transistor (452), and an undoped dielectric portion (462) adjacent the gate end. According to another embodiment, the drain end of the conductive gate (434) is disposed on top of a thick insulator region (432) that also acts to mitigate the high electric fields present when the transistor is subjected to a high voltage transient.

Claims

1. A process for fabricating an insulated-gate field-effect transistor having reduced gate insulator stress, comprising the steps of:

forming a first tank region in which the semiconductor portions of the insulated-gate field-effect transistor are to be contained;

forming a second tank region of a second conductivity type opposite the conductivity type of the first tank region, and to be contained within the first tank region; and

forming a control gate to be insulatively adjacent a semiconductor channel region of the transistor so as to control the conductance thereof after the process is completed, said control gate formed such that a lateral margin of the second tank region is beneath the first portion of the control gate;

selectively modifying a first portion of the control gate to be substantially conductive;

during said step of selectively modifying, masking a second portion of the control gate such that it will remain substantially nonconductive;

forming a semiconductor source region adjacent the first portion of the control gate; and

forming a semiconductor drain region substantially adjacent the second portion of the control gate.

2. The process of claim 1, wherein said step of selectively modifying comprises doping the first portion with a dopant.