Trench isolation using gated sidewalls

• US 5,275,965 A
• Filed: 11/25/1992
• Issued: 01/04/1994
• Est. Priority Date: 11/25/1992
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Semiconductor, Inc. (Micron Technology, Inc.)
• Inventors: Manning, Monte
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US07/981,631
• Time in Patent Office: 405 Days
• Field of Search: 437/67, 437/203, 437/228, 437/61, 257/302, 257/330, 257/332
• US Class Current: 438/430
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence

Abstract

The invention is directed to improving trench isolation between active devices by using gated sidewalls. In a first embodiment, trenches are etched into the substrate and a thin oxide film is formed to passivate the trench sidewalls and serve as a sidewall gate oxide. The oxide is removed from the bottom of the trench while leaving the sidewall oxide intact. A thin poly layer is formed into the trench so that the thin poly does not completely fill the trench, yet the thin poly film will overlie the oxide sidewalls and make contact to the exposed substrate at the bottom of the trench. The trench is then completely filled with a conformal oxide that is planarized. The planarized oxide is etched during thermal oxide etch and a sacrificial oxide is grown. Following threshold adjust implants, the sacrificial oxide is removed and the final gate sidewall oxide is formed. In a second embodiment, the process steps vary by leaving the thin oxide film at the bottom of the trench and then forming a thin poly film over the thin film oxide. The steps then continue as in the first embodiment and the thin poly in the trench is later tied to the substrate at points on the die external from the trench.

Claims

1. A process for forming self aligned gated sidewall trench isolation between active devices in a semiconductor device fabricated on a starting substrate, said process comprising:

a) forming trenches into said starting substrate, said starting substrate being masked with patterned insulating layers;

b) forming a conformal insulating layer to the sidewalls and bottom of said trench;

c) removing said conformal insulating layer from said bottom of said trench;

d) forming a conductive material layer over the sidewalls and bottom of said trench;

e) forming a planarized insulating layer inside said trench while exposing portions of said conductive layer;

f) removing said exposed portions of the conductive layer;

g) removing said patterned insulating layers thereby exposing portions of said starting substrate and exposing the upper ends of said conductive layer;

h) forming a sacrificial insulating layer over said exposed substrate portions and said conductive layer'"'"'s exposed upper ends;

i) conductively doping said starting substrate;

j) removing said sacrificial insulating layer; and

k) forming a gate insulating layer over said starting substrate for said active devices.

2. The process as recited in claim 1, wherein said starting substrate is silicon.

3. The process as recited in claim 1, wherein said conformal insulating layer, said planarized insulating layer, said sacrificial insulating layer, and said gate insulating layer are oxides.

4. The process as recited in claim 1, wherein said conductive layer is in-situ doped polysilicon.

5. The process as recited in claim 4, wherein said polysilicon is doped to a n-type conductivity.

6. The process as recited in claim 4, wherein said polysilicon is doped to a p-type conductivity.

7. The process as recited in claim 5, wherein said polysilicon is doped by phosphorous.

8. The process as recited in claim 5, wherein said polysilicon is doped by arsenic.

9. The process as recited in claim 6, wherein said polysilicon is doped by boron.

10. The process as recited in claim 7, wherein said conformal oxide is approximately 250 Å

thick.

11. The process as recited in claim 4, wherein said polysilicon is approximately 500 Å

thick.

12. A process for forming self aligned gated sidewall trench isolation between active devices in a semiconductor device fabricated on a starting silicon substrate, said process comprising:

a) forming trenches into said starting silicon substrate, said starting silicon substrate being masked with patterned nitride and oxide layers;

b) forming a conformal oxide layer to the sidewalls and bottom of said trench;

c) removing said conformal oxide layer from said bottom of said trench;

d) forming a conductively doped polysilicon layer over the sidewalls and bottom of said trench;

e) forming a planarized oxide layer inside said trench while exposing portions of said conductively doped polysilicon layer;

f) removing said exposed portions of the conductively doped polysilicon layer;

g) removing said patterned nitride and oxide layers thereby exposing portions of said starting silicon substrate and exposing the upper ends of said conductively doped polysilicon layer;

h) forming a sacrificial oxide layer over said exposed starting silicon substrate portions and said conductively doped polysilicon layer'"'"'s exposed upper ends;

i) conductively doping said starting silicon substrate;

j) removing said sacrificial oxide layer; and

k) forming a gate oxide layer over said starting silicon substrate for said active devices.

13. The process as recited in claim 12, wherein said conductively doped polysilicon layer is in-situ doped to a n-type conductivity.

14. The process as recited in claim 12, wherein said conductively doped polysilicon layer is in-situ doped to a p-type conductivity.

15. The process as recited in claim 13, wherein said polysilicon is doped by phosphorous.

16. The process as recited in claim 13, wherein said polysilicon is doped by arsenic.

17. The process as recited in claim 14, wherein said polysilicon is doped by boron.

18. The process as recited in claim 12, wherein said conformal oxide is approximately 250 Å

thick.

19. The process as recited in claim 12, wherein said conductively doped polysilicon is approximately 500 Å

thick.

20. A process for forming self aligned gated sidewall trench isolation between active devices in a semiconductor device fabricated on a starting substrate, said process comprising:

a) forming trenches into said starting substrate, said starting substrate being masked with patterned insulating layers;

b) forming a conformal insulating layer to the sidewalls and bottom of said trench;

c) forming a conductive material layer over the sidewalls and bottom of said trench;

d) forming a planarized insulating layer inside said trench while exposing portions of said conductive layer;

e) removing said exposed portions of the conductive layer;

f) removing said patterned insulating layers thereby exposing portions of said starting substrate and exposing the upper ends of said conductive layer;

g) forming a sacrificial insulating layer over said exposed substrate portions and said conductive layer'"'"'s exposed upper ends;

h) conductively doping said starting substrate;

i) removing said sacrificial insulating layer; and

j) forming a gate insulating layer over said starting substrate for said active devices.

21. The process as recited in claim 20, wherein said starting substrate is silicon.

22. The process as recited in claim 20, wherein said conformal insulating layer, said planarized insulating layer, said sacrificial insulating layer, and said gate insulating layer are oxides.

23. The process as recited in claim 20, wherein said conductive layer is in-situ doped polysilicon.

24. The process as recited in claim 23, wherein said polysilicon is doped to a n-type conductivity.

25. The process as recited in claim 23, wherein said polysilicon is doped to a p-type conductivity.

26. The process as recited in claim 24, wherein said polysilicon is doped by phosphorous.

27. The process as recited in claim 24, wherein said polysilicon is doped by arsenic.

28. The process as recited in claim 25, wherein said polysilicon is doped by boron.

29. The process as recited in claim 20, wherein said conformal insulating layer comprises an oxide layer which is approximately 250 Å

thick.

30. The process as recited in claim 23, wherein said polysilicon is approximately 500 Å

thick.

31. A process for forming self aligned gated sidewall trench isolation between active devices in a semiconductor device fabricated on a starting substrate, said process comprising:

a) forming trenches into said starting substrate, said starting substrate being masked with patterned insulating layers;

b) forming a conformal insulating layer to the sidewalls and bottom of said trench;

c) forming a conductive material layer over the sidewalls and bottom of said trench;

d) forming a planarized insulating layer inside said trench while exposing portions of said conductive layer;

e) removing said exposed portions of the conductive layer;

f) removing said patterned insulating layers thereby exposing portions of said starting substrate and exposing the upper ends of said conductive layer;

g) conductively doping said starting substrate.

32. The process as recited in claim 31, wherein threshold adjust implants are performed through said conformal insulating layer.

33. The process as recited in claim 31, wherein said starting substrate is silicon.

34. The process as recited in claim 31, wherein said conformal insulating layer and said planarized insulating layer are oxides.

35. The process as recited in claim 31, wherein said conductive layer is in-situ doped polysilicon.

36. The process as recited in claim 35, wherein said polysilicon is doped to a n-type conductivity.

37. The process as recited in claim 35, wherein said polysilicon is doped to a p-type conductivity.

38. The process as recited in claim 36, wherein said polysilicon is doped by phosphorous.

39. The process as recited in claim 36, wherein said polysilicon is doped by arsenic.

40. The process as recited in claim 37, wherein said polysilicon is doped by boron.

41. The process as recited in claim 31, wherein said conformal insulating layer comprises an oxide layer which is approximately 250 Å

thick.

42. The process as recited in claim 35, wherein said polysilicon is approximately 500 Å

thick.

43. A process for forming self aligned gated sidewall trench isolation between active devices in a semiconductor device fabricated on a starting silicon substrate, said process comprising:

a) forming trenches into said starting silicon substrate, said starting silicon substrate being masked with patterned nitride and oxide layers;

b) forming a conformal oxide layer to the sidewalls and bottom of said trench;

c) forming a conductively doped polysilicon layer over the sidewalls and bottom of said trench;

d) forming a planarized oxide layer inside said trench while exposing portions of said conductively doped polysilicon layer;

e) removing said exposed portions of the conductively doped polysilicon layer;

f) removing said patterned nitride and oxide layers thereby exposing portions of said starting silicon substrate and exposing the upper ends of said conductively doped polysilicon layer;

g) forming a sacrificial oxide layer over said exposed starting silicon substrate portions and said conductively doped polysilicon layer'"'"'s exposed upper ends;

h) conductively doping said starting silicon substrate;

i) removing said sacrificial oxide layer; and

j) forming a gate oxide layer over said starting silicon substrate for said active devices.

44. The process as recited in claim 43, wherein said conductively doped polysilicon layer is in-situ doped to a n-type conductivity.

45. The process as recited in claim 43, wherein said conductively doped polysilicon layer is in-situ doped to a p-type conductivity.

46. The process as recited in claim 44, wherein said polysilicon is doped by phosphorous.

47. The process as recited in claim 44, wherein said polysilicon is doped by arsenic.

48. The process as recited in claim 45, wherein said polysilicon is doped by boron.

49. The process as recited in claim 43, wherein said conformal oxide layer is approximately 250 Å

thick.

50. A process for forming self aligned gated sidewall trench isolation between active devices in a semiconductor device fabricated on a starting silicon substrate, said process comprising:

a) forming trenches into said starting silicon substrate, said starting silicon substrate being masked with patterned nitride and oxide layers;

b) forming a conformal oxide layer to the sidewalls and bottom of said trench;

c) forming a conductively doped polysilicon layer over the sidewalls and bottom of said trench;

d) forming a planarized oxide layer inside said trench while exposing portions of said conductively doped polysilicon layer;

e) removing said exposed portions of the conductively doped polysilicon layer;

f) removing said patterned nitride and oxide layers thereby exposing portions of said starting silicon substrate and exposing the upper ends of said conductively doped polysilicon layer;

g) conductively doping said starting silicon substrate.

51. The process as recited in claim 50, wherein threshold adjust implants are performed through said conformal oxide layer.

52. The process as recited in claim 50, wherein said conductively doped polysilicon layer is in-situ doped to a n-type conductivity.

53. The process as recited in claim 50, wherein said conductively doped polysilicon layer is in-situ doped to a p-type conductivity.

54. The process as recited in claim 52, wherein said polysilicon is doped by phosphorous.

55. The process as recited in claim 52, wherein said polysilicon is doped by arsenic.

56. The process as recited in claim 53, wherein said polysilicon is doped by boron.

57. The process as recited in claim 50, wherein said conformal oxide is approximately 250 Å

thick.