Integrated semiconductor circuit
First Claim
1. An integrated semiconductor circuit, comprising:
- a plurailty of word lines and a plurality of bit lines, each bit line including a pair of complementary bit line halves;
a memory region including at least one memory cell field, each memory cell field including a plurailty of memory cells addressable by said word lines and said bit lines;
A plurality of sense amplifiers, each connected to a respective bit line;
A plurality of logic units, each connected to a respective sense amplifier for digitally processing data received from said sense amplifiers; and
mode selecting means connected to said logic units for selecting different operating modes of said logic units by means of mode select signals;
mode select signal deactivating means connected to said mode selecting means for deactivating said mode select signals;
including in each of said logic units;
a first and a second transistor, each having a source, a drain and a gate, for logic inversion of said data; and
a charge capacitor having a first and a second terminal, wherein the drain of said first and second transistor is connected to the first terminal of said charge capacitor, the source of said first transistor is connected to one of said bit line halves, and the source of the second transistor is connected to the other one of said bit line halves, and wherein said mode select signals include two first mode select signals.
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Accused Products
Abstract
An integrated semiconductor circuit includes word lines and bit lines. A memory region has at least one memory cell field with memory cells addressable through the word lines and the bit lines, and a number of evaluator circuits corresponding to the number of the bit lines. Each of the evaluator circuits is connected with one of the bit lines and divides the one bit line into two at least approximately identical bit line halves. Logic units of a block perform digital processing of data read-out of the memory region through the bit lines and evaluated. Each of the logic units is connected to the two bit line halves of one of the bit lines. Various operating modes of the block of logic units are selected with mode select signals.
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Citations
17 Claims
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1. An integrated semiconductor circuit, comprising:
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a plurailty of word lines and a plurality of bit lines, each bit line including a pair of complementary bit line halves; a memory region including at least one memory cell field, each memory cell field including a plurailty of memory cells addressable by said word lines and said bit lines; A plurality of sense amplifiers, each connected to a respective bit line; A plurality of logic units, each connected to a respective sense amplifier for digitally processing data received from said sense amplifiers; and mode selecting means connected to said logic units for selecting different operating modes of said logic units by means of mode select signals;
mode select signal deactivating means connected to said mode selecting means for deactivating said mode select signals;
including in each of said logic units;
a first and a second transistor, each having a source, a drain and a gate, for logic inversion of said data; and
a charge capacitor having a first and a second terminal, wherein the drain of said first and second transistor is connected to the first terminal of said charge capacitor, the source of said first transistor is connected to one of said bit line halves, and the source of the second transistor is connected to the other one of said bit line halves, and wherein said mode select signals include two first mode select signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification