Integrated semiconductor circuit

• US 5,276,643 A
• Filed: 11/26/1991
• Issued: 01/04/1994
• Est. Priority Date: 08/11/1988
• Status: Expired due to Term

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Siemens AG
• Inventors: Kowarik, Oskar, Hoffmann, Kurt, Kraus, Rainer
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US07/799,907
• Time in Patent Office: 770 Days
• Field of Search: 365/207, 365/208, 365/201, 365/203, 365/205, 365/185, 365/210, 365/189.8, 365/189.5
• US Class Current: 365/189.08
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

An integrated semiconductor circuit includes word lines and bit lines. A memory region has at least one memory cell field with memory cells addressable through the word lines and the bit lines, and a number of evaluator circuits corresponding to the number of the bit lines. Each of the evaluator circuits is connected with one of the bit lines and divides the one bit line into two at least approximately identical bit line halves. Logic units of a block perform digital processing of data read-out of the memory region through the bit lines and evaluated. Each of the logic units is connected to the two bit line halves of one of the bit lines. Various operating modes of the block of logic units are selected with mode select signals.

Claims

1. An integrated semiconductor circuit, comprising:

a plurailty of word lines and a plurality of bit lines, each bit line including a pair of complementary bit line halves;

a memory region including at least one memory cell field, each memory cell field including a plurailty of memory cells addressable by said word lines and said bit lines;

A plurality of sense amplifiers, each connected to a respective bit line;

A plurality of logic units, each connected to a respective sense amplifier for digitally processing data received from said sense amplifiers; and

mode selecting means connected to said logic units for selecting different operating modes of said logic units by means of mode select signals;

mode select signal deactivating means connected to said mode selecting means for deactivating said mode select signals;

including in each of said logic units;

a first and a second transistor, each having a source, a drain and a gate, for logic inversion of said data; and

a charge capacitor having a first and a second terminal, wherein the drain of said first and second transistor is connected to the first terminal of said charge capacitor, the source of said first transistor is connected to one of said bit line halves, and the source of the second transistor is connected to the other one of said bit line halves, and wherein said mode select signals include two first mode select signals.

2. An integrated semiconductor circuit according to claim 1 including a common line common to said logic units, having a charge state, means for precharging said common line to a fixed potential, a third transistor having a source, a drain, and a gate in each of said logic units connected with its source and drain between said first terminal of said charge capacitor and said common line, a discriminator circuit connected to said common line ror recognizing the charge state of said common line, including a second mode in said mode select signals connected to the gate of said third transistor for performing a number equal to "i" of logic comparisons between the data received from said sense amplifiers and the state of said common line;

wherein the number "i" is equal to the plurality of logic units.

3. Integrated semiconductor circuit according to claim 2, including a support capacitor connected between said common line and a fixed potential.

4. Integrated semiconductor circuit according to claim 2, including two first and two second transfer transistors having channels and gates,

one of said first and one of said second transfer transistors being connected with the channels thereof in series between the drains of said two first transistors and one of said two bit line halves, the other of said first and the other of said third transfer transistors being connected with the channels thereof in series between the drains of said two first transistors and the other of said two bit line halves;

said mode select signals including two second mode select signals each being fed to the gate of a respective one of said two second transfer transistors;

the gate of said one first transfer transistor being connected to said other bit line half, and the gate of said other first transfer transistor being connected to said one bit line half.

5. Integrated semiconductor circuit according to claim 4, including two buffer store capacitors having first and second electrodes,

the gates of said two first transfer transistors each being connected to the first electrode of a respective one of said two buffer store capacitors, defining two respective memory nodes therebetween;

the second electrodes of said buffer store capacitors being connected to a fixed potential;

memory transistors having channels and gates, each of said channels of said memory transistors being connected between a respective one of said two memory nodes and a corresponding one of said bit line halves; and

said mode select signals including a fourth mode select signal connected to the gates of said memory transistors.

6. Integrated semiconductor circuit according to claim 4 including two buffer store capacitors having first and second electrodes,

the gates of said two first transfer transistors each being connected to the first electrode of a respective one of said two buffer store capacitors, defining two respective memory nodes therebetween;

the second electrodes of said buffer store capacitors being connected to a fixed potential;

memory transistors having channels and gates, each of said channels of said memory transistors being connected between a respective one of said two memory nodes and a corresponding one of said bit line halves; and

said mode select signals including two third mode select. signals each being connected to the gate of a respective one of said memory transistors.

7. Integrated semiconductor circuit according to claim 5, wherein each of said logic units includes a shift transistor having a channel and a gate,

the channel of said shift transistor being connected between the first terminal of said charge capacitor and one of said bit line halves of an adjacent bit line;

and

said mode select signals including a fifth mode select signal fed to the gate of said shift transistor as a shift signal.

8. Integrated semiconductor circuit according to claim 6, wherein each of said logic units includes a shift transistor having a channel and a gate,

the channel of said shift transistor being connected between the first terminal of said charge capacitor and one of said bit line halves of an adjacent bit line;

and

said mode select signal including a fifth mode select signal fed to the gate of said shift transistor as a shift signal.

9. Integrated semiconductor circuit according to claim 7, wherein said logic units and said bit lines are disposed in a given order from a first logic unit and a first bit line to a last logic unit and a last bit line, and the first terminal of said charge capacitor is connected through said shift transistor in said first logic unit with said last bit line, as seen in said given order.

10. Integrated semiconductor circuit according to claim 8, wherein said logic units and said bit lines are disposed in a given order from a first logic unit and a first bit line to a last logic unit and a last bit line, and the first terminal of said charge capacitor is connected through said shift transistor in said first logic unit with said last bit line, as seen in said given order.

11. Integrated semiconductor circuit according to claim 7, wherein said logic units and said bit lines are disposed in a given order from a first logic unit and a first bit line to a last logic unit and a last bit line, and the first terminal of said charge capacitor is connected through said shift transistor in said first logic unit with said last bit-line, as seen in said given order.

12. Integrated semiconductor circuit according to claim 8, wherein said logic units and said bit lines are disposed in a given order from a first logic unit and a first bit line to a last logic unit and a last bit line, and the first terminal of said charge capacitor is connected through said shift transistor in said last logic unit with said first bit line, as seen in said given order.

13. Integrated semiconductor circuit according to claim 5, wherein said buffer store capacitors are stray capacitances of said first transfer transistors.

14. Integrated semiconductor circuit according to claim 1, including static memory cells providing said charge capacitors of each of said logic units.

15. Integrated semiconductor circuit according to claim 1, wherein said memory cells are dynamic random access memory cells.

16. Integrated semiconductor circuit according to claim 1, wherein said memory cells are static random access memory cells.

17. Integrated semiconductor circuit according to claim 1, wherein said memory cells are memory cells of the non-volatile type.