Dynamic-type semiconductor memory device having staggered activation of column groups

• US 5,276,649 A
• Filed: 08/12/1991
• Issued: 01/04/1994
• Est. Priority Date: 03/16/1989
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Tobita, Youichi, Tokami, Kenji, Hoshita, Tetsushi
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): WHITFIELD, MICHAEL
• Application Number:
  US07/746,092
• Time in Patent Office: 876 Days
• Field of Search: 365/63, 365/227, 365/194, 365/205, 365/206, 365/207, 365/208, 365/233, 365/230.03, 365/230.04, 365/230.06, 365/230.08
• US Class Current: 365/206
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A semiconductor memory device includes a memory cell array block (1; MB1 to MB16) having a first column group (area I) and a second column group (area II). The device also includes sense amplifiers (10-1, 10-2, 10-3 . . . ) provided for each column to detect and amplify a read-out voltage on associated columns. The device further includes a control circuit (20) for activating the sense amplifiers for the first column group and the sense amplifiers for the second column group at different timings to reduce peak current in sensing operation. The control circuit operates in response to a column designating signal to activate first the sense amplifiers for the column group including a column connecting thereto a selected memory cell. The column designating signal includes an externally applied column address bit. The column address bit is supplied to the device simultaneous with row address bits in an address multiplexing memory device. The first column group (BL0, BL0, BL2, BL2) includes a plurality of bit line pairs having at least one twisted portions. The second column group (BL1, BL1) includes a plurality of bit line pairs having no or one or more twisted portion. Bit line pairs of the first column group and bit line pairs of the second column group are arranged alternately.

Claims

1. A semiconductor memory device for accessing a memory cell, in response to applied address signals for designating the memory cell for data reading or data writing, comprising:

a cell array having a plurality of memory cells arranged in a matrix of rows and columns, said cell array including a first group of columns and a second group of columns;

first sense amplifier means provided for each respective column of said first group of columns for sensing and amplifying signal potentials on associated columns;

second sense amplifier means provided for each respective column of said second group of columns for sensing and amplifying signal potentials on associated columns;

row selection means responsive to a first address signal for selecting a corresponding row in said cell array;

buffer means responsive to a second address signal for generating a column group designating signal and applying said column group designating signal to column selection means, said first and second address signals being simultaneously applied to said semiconductor memory device;

activation means responsive to said column group designating signal for activating said first sense amplifier means and said second sense amplifier means at different timings,

said activation means including means for activating first the sense amplifiers provided for the columns included in the column group designated by said column group designating signal; and

said column selection means being responsive to said second address signal and a third address signal for selecting a corresponding column in said cell array, said third address signal and said first and second address signals being applied at different timings.

2. A memory device according to claim 1, wherein said first group of columns comprises a plurality of bit line pairs each having at least one twisted portion thereon, and said second group of columns comprises a plurality of bit line pairs having no twisted portions thereon.

3. A semiconductor memory device according to claim 1, wherein said activation means comprises,

delay means for delaying a received sense amplifier activating signal by a predetermined time,

first means responsive to said column group designating signal for selectively providing one of an output of said delay means and said sense amplifier activating signal to said first sense amplifier means, and

second means responsive to said column group designating signal for selectively providing one an output of said delay means and said sense amplifier activating signal to the second sense amplifier means.

4. A semiconductor memory device according to claim 1,

wherein said first sense amplifier means and said second sense amplifier means are arranged in two lines, and said first sense amplifier means are disposed on one line and said second sense amplifier means are disposed on the other line.

5. A memory device according to claim 1 wherein said first group of columns comprises a first plurality of bit line pairs each having at least one twisted portion thereon and said second group of columns comprises a second plurality of bit line pairs, said bit line pairs of said first group and bit line pairs of said second group being alternately arranged.

6. A semiconductor memory device according to claim 5,

wherein said first amplifier means are disposed on one end of said bit line pairs, and said second sense amplifier means are disposed on the opposite end of said bit line pairs.

7. A memory device according to claim 5, wherein said first group of columns comprises a first plurality of bit line pairs each having at least one twisted portion thereon, and said second group of columns comprises a second plurality of bit line pairs having one twisted portion thereon.

8. A memory device according to claim 5, wherein said first group of columns comprises a first plurality of bit line pairs each having at least one twisted portion thereon, and said second group of columns comprises a second plurality of bit line pairs having more than one twisted portion thereon.

9. A semiconductor memory device according to claim 1, wherein said activation means comprises,

first gate means, activated in response to at least said column group designating signal and an activation signal, for passing a sense amplifier activating signal,

delay means for delaying said sense amplifier activating signal by a predetermined time period,

second gate means, activated in response to at least an inverted signal of said column group designating signal and a delayed activation signal, for passing an output of delay means,

third gate means responsive to at least an activating signal from at least either one of said first and second gate means for deriving an activating signal to transfer the same to said first sense amplifier means,

fourth gate means, activated in response to at least the inverted signal of said column group designating signal and said activation signal, for passing the same as a sense amplifier activating signal,

fifth gate means, activated in response to at least said column group designating signal and said delayed activation signal, for passing said output of delay means, and

sixth gate means responsive to at least an activating signal from at least either one of said fourth and fifth gate means for deriving an activating signal to transfer the same to said second sense amplifier means.

10. A semiconductor memory device according to claim 1, wherein said activation means comprises,

first AND gate means activated in response to at least said column group designating signal for passing a sense amplifier activating signal,

delay means for delaying said sense amplifier activating signal by a predetermined time period,

second AND gate means activated in response to at least an inverted signal of said column group designating signal for passing an output of delay means,

first OR gate means responsive to at least an activating signal from at least either one of said first and second gate means for deriving an activating signal to transfer the same to said first sense amplifier means,

fourth AND gate means activated in response to at least the inverted signal of said column group designating signal for passing the same as a sense amplifier activating signal,

fifth AND gate means activated in response to at least said column group designating signal for passing said output of delay means, and

second OR gate means responsive to at least an activating signal from at least either one of said fourth and fifth gate means for deriving an activating signal to transfer the same to said second sense amplifier means.

11. An address multiplexing semiconductor memory device, comprising;

a cell array including a plurality of memory cells arranged in rows and columns;

row selection means responsive to a first address signal for selecting a corresponding row in said cell array, said first address signal being applied to said memory device at a first timing;

buffer means responsive to a second address signal for generating a column group designating signal and applying said column group designating signal to column selection means, said first and second address being simultaneously applied to said semiconductor memory device;

sense amplifier means provided for each respective column of said cell array for sensing and amplifying a signal potential on an associated column;

activation means responsive to said column group designating signal for activating said sense amplifier means,

column selection means responsive to said second address signal and a third address signal for selecting a corresponding column in said cell array, said third address signal being applied at a second timing different from said first timing.

12. In a method of operating a semiconductor memory device comprising a cell array having a plurality of memory cells arranged in a matrix of rows and columns wherein said columns are grouped into a first group of columns and a second group of columns, first sense amplifiers provided for the columns of said first group for sensing and amplifying signal potentials on associated columns and second sense amplifiers provided for the column of said second group for sensing and amplifying signal potentials on associated columns, including row selection means and column selection means a method of driving the sense amplifiers comprising the steps of:

applying first and second address signals simultaneously to said semiconductor memory device;

generating a column group designating signal, in response to said second address signal;

applying said column group designating signal to said column selection means;

activating, in response to said column group designating signal, said first sense amplifiers and said second sense amplifiers at different timings;

wherein sense amplifiers provided for the columns corresponding to a column group designated by said column group designating are first activated,

said row selection means are responsive to said first address signal applied to said semiconductor memory device to designate a row in said cell array at a first timing, and

said second address signal constitutes a column address signal for designating a column in said cell array when combined with a third address signal applied at a second timing different from said first timing.

13. A method according to claim 12, wherein said activating step comprises the steps of:

delaying a sense amplifier activating signal,

passing either one of said sense amplifier activating signal and said delayed sense amplifier activating signal in response to said column group designating signal, for transferring the same to said first sense amplifiers, and

passing either one of said sense amplifier activating signal and said delayed sense amplifier activating signal in response to said column group designating signal, for transferring the same to said second sense amplifiers, wherein when said sense amplifier activating signal is transferred to sense amplifiers of one of the groups, said delayed sense amplifier activating signal is transferred to sense amplifiers of the other group.

14. In a method of operating a semiconductor memory device including a cell array having a plurality of memory cells arranged in a matrix of rows and columns wherein said columns comprise a first group of bit line pairs each having at least one crossing portion therein and a second group of bit line pairs each having no crossing therein, first sense amplifiers provided for the bit line pairs of said first group for sensing and amplifying signal potentials on associated bit line pairs, and second sense amplifier provided for the columns of said second group for sensing and amplifying signal potentials on associated bit line pairs, and wherein said bit line pairs of said first group and bit line pairs of said second group are arranged alternately in said cell array including row selection means and column selection means, a method of driving the sense amplifiers comprising the steps of:

applying first and second address signals simultaneously to said semiconductor memory device;

generating a column group designating signal, in response to said second address signal,

applying said column group designating signal to said column selection means;

activating, in response to said group designating signal, said first sense amplifiers and said second sense amplifier at different timings;

wherein sense amplifiers corresponding to a column group provided for the bit line pairs designated by said group designating signal are first activated,

said row selection means are responsive to said first address signal applied to said semiconductor memory device at a first timing to designate a row in said cell array, and

said second address signal constitutes a column address signal for designating a column in said cell array when combined with a third address signal applied thereto at a second timing different from said first timing.

15. A method according to claim 14, wherein said activating step comprises the steps of:

delaying a sense amplifier activating signal,

passing either one of said sense amplifier activating signal and said delayed sense amplifier activating signal in response to said group designating signal, for transferring the same to said first sense amplifiers, and

passing either one of said sense amplifier activating signal and said delayed sense amplifier activating signal in response to said group designating signal, for transferring the same to said second sense amplifiers, wherein when said sense amplifier activating signal is transferred to sense amplifiers of one of the groups, said delayed sense amplifier activating signal is transferred to sense amplifiers of the other group.

16. A method for operating a semiconductor memory device comprising a cell array including a plurality of memory cells arranged in rows and columns including column selection means, comprising the steps of:

receiving a first address signal for generating a row designating signal for designating a row in said cell array;

receiving a second address signal simultaneously with said first address signal;

generating a column group designating signal in response to said second address signal;

applying said column group designating signal to said column selection means;

receiving a third address signal at a timing different from that of said first and second address signals to combine said third address signal with said second address signal to generate a column designating signal designating a column in said cell array; and

activating sense amplifiers in a column group designated by said column group designating signal before activating sense amplifiers in column groups not designated by said column group designating signal.